Datasheet > K4X56163PE-LG000

K4X56163PE-LG000

更新时间： 2024-02-19 01:21:15

品牌	Logo	应用领域
三星 - SAMSUNG		/
页数	文件大小	规格书
48页	698K
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数据手册

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K4X56163PE-LG000 数据手册

K4X56163PE-L(F)G

Mobile-DDR SDRAM

16M x16 Mobile DDR SDRAM

FEATURES

• 1.8V power supply, 1.8V I/O power

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Four banks operation

• Differential clock inputs(CK and CK)

• MRS cycle with address key programs

- CAS Latency ( 3 )

- Burst Length ( 2, 4, 8 )

- Burst Type (Sequential & Interleave)

- Partial Self Refresh Type ( Full, 1/2, 1/4 array )

- Internal Temperature Compensated Self Refresh

- Driver strength ( 1, 1/2, 1/4, 1/8 )

• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).

• Data I/O transactions on both edges of data strobe, DM for masking.

• Edge aligned data output, center aligned data input.

• No DLL; CK to DQS is not synchronized.

• LDM/UDM for write masking only.

• 7.8us auto refresh duty cycle.

• CSP package.

Operating Frequency

DDR200

DDR133

Speed @CL3

*CL : CAS Latency

100Mhz

66Mhz

Column address configuration

Organization

Row Address

Column Address

16Mx16

A0 ~ A12

A0-A8

DM is internally loaded to match DQ and DQS identically.

March 2004

12 3 4 5 6 7...48

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K4X56163PG-FGC30	SAMSUNG	获取价格	DDR DRAM, 16MX16, 6ns, CMOS, PBGA60, LEAD FREE, FBGA-60
K4X56163PG-FGCA	SAMSUNG	获取价格	DDR DRAM, 16MX16, 6ns, CMOS, PBGA60,
K4X56163PG-FGCA0	SAMSUNG	获取价格	DDR DRAM, 16MX16, 6ns, CMOS, PBGA60, LEAD FREE, FBGA-60
K4X56163PG-LGC30	SAMSUNG	获取价格	DDR DRAM, 16MX16, 6ns, CMOS, PBGA60, FBGA-60
K4X56163PG-LGCA0	SAMSUNG	获取价格	DDR DRAM, 16MX16, 6ns, CMOS, PBGA60, FBGA-60