Datasheet > K4S561632D-NL1H0

K4S561632D-NL1H0

更新时间： 2024-01-15 16:57:45

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器光电二极管
页数	文件大小	规格书
9页	46K
描述
Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, STSOP2-54

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K4S561632D-NL1H0 数据手册

K4S561632D

CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Version

Parameter

Symbol

Test Condition

Unit Note

-60

-7C

-75

-1H -1L

Burst length = 1

tRC ³ tRC(min)

IO = 0 mA

Operating current

(One bank active)

ICC1

150 110

100

100 100

ICC2P

CKE £ VIL(max), tCC = 10ns

Precharge standby cur-

rent in power-down mode

ICC2PS

CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns

ICC2N

Precharge standby cur-

rent in non power-down

mode

Input signals are changed one time during 20ns

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC2NS

ICC3P

CKE £ VIL(max), tCC = 10ns

Active standby current in

power-down mode

ICC3PS

CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns

ICC3N

Active standby current in

non power-down mode

(One bank active)

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC3NS

IO = 0 mA

Operating current

(Burst mode)

Page burst

ICC4

180 140

220 220

140

130 130

190 190

4banks Activated.

tCCD = 2CLKs

Refresh current

ICC5

ICC6

tRC ³ tRC(min)

200

Self refresh current

CKE £ 0.2V

1.5

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S561632D-NC**

4. K4S561632D-NL**

5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).

Rev. 0.1 Aug. 2002

1...3 4 567 8 9

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