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K4S561632D-NL1H0 PDF预览

K4S561632D-NL1H0

更新时间： 2024-01-11 22:59:35
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管
页数 文件大小 规格书
9页 46K
描述
Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, STSOP2-54

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K4S561632D-NL1H0 数据手册

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K4S561632D  
CMOS SDRAM  
SIMPLIFIED TRUTH TABLE  
A11,A12,  
A9 ~ A0  
Command  
CKEn-1  
CKEn  
CS  
L
RAS  
L
CAS  
WE  
L
DQM  
X
BA0,1  
A10/AP  
OP code  
X
Note  
Register  
Refresh  
Mode register set  
Auto refresh  
H
H
X
H
L
L
L
1,2  
3
L
L
H
X
Entry  
Exit  
3
Self  
refresh  
L
H
L
H
X
L
H
X
H
H
X
H
3
L
H
X
X
3
Bank active & row addr.  
H
H
X
X
X
X
V
V
Row address  
Column  
address  
(A0 ~ A8 )  
Read &  
column address  
Auto precharge disable  
Auto precharge enable  
Auto precharge disable  
Auto precharge enable  
L
H
L
4
4,5  
4
L
L
H
H
L
L
H
L
Column  
address  
(A0 ~ A8 )  
Write &  
column address  
H
X
X
V
H
X
L
4,5  
6
Burst stop  
Precharge  
H
H
X
X
L
L
H
L
H
H
L
L
X
X
Bank selection  
All banks  
V
X
X
H
H
L
X
V
X
X
H
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry  
H
L
X
Clock suspend or  
active power down  
X
X
Exit  
L
H
L
X
H
L
X
X
Entry  
H
Precharge power down mode  
H
L
Exit  
L
H
X
X
V
X
DQM  
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command  
(V=Valid, X=Don't care, H=Logic high, L=Logic low)  
Notes :  
1. OP Code : Operand code  
A0 ~ A11,A12 & BA0 ~ BA1 : Program keys. (@ MRS)  
2. MRS can be issued only at all banks precharge state.  
A new command can be issued after 2 CLK cycles of MRS.  
3. Auto refresh functions are as same as CBR refresh of DRAM.  
The automatical precharge without row precharge command is meant by "Auto".  
Auto/self refresh can be issued only at all banks precharge state.  
4. BA0 ~ BA1 : Bank select addresses.  
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.  
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.  
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.  
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.  
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.  
5. During burst read or write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the associated bank can be issued at tRP after the end of burst.  
6. Burst stop command is valid at every burst length.  
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),  
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)  
Rev. 0.1 Aug. 2002  
1...6789

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与K4S561632D-NL1H0相关器件

型号 品牌 获取价格 描述 数据表
K4S561632D-NL1L SAMSUNG

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 		Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.300 X 0.551 INCH, 0.50 MM PITCH, STSOP2-54
K4S561632D-NL1L0 SAMSUNG

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 		Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, STSOP2-54
K4S561632D-NL60 SAMSUNG

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 		Synchronous DRAM, 16MX16, 5ns, CMOS, PDSO54, 0.300 X 0.551 INCH, 0.50 MM PITCH, STSOP2-54
K4S561632D-NL600 SAMSUNG

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 		Synchronous DRAM, 16MX16, 5ns, CMOS, PDSO54, STSOP2-54
K4S561632D-NL75 SAMSUNG

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 		Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.300 X 0.551 INCH, 0.50 MM PITCH, STSOP2-5
K4S561632D-NL7C0 SAMSUNG

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 		Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, STSOP2-54
K4S561632D-TC/L1H SAMSUNG

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 		256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL
K4S561632D-TC/L1L SAMSUNG

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 		256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL
K4S561632D-TC/L60 SAMSUNG

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 		256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL
K4S561632D-TC/L75 SAMSUNG

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 		256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

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