K4E171613(4)C
CMOS DRAM
Low Power 1M x 16Bit CMOS Dynamic RAM with EDO
DESCRIPTION
This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs with low operating & self refresh voltage. Extended Data Out
Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+3.0V/
+2.5V), access time (-60/-70), power consumption and package type(TSOP-Il) are optional features of this family. All of this family have
CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-ver.
This 1Mx16 EDO Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as buffer memory or main memory unit for mobile system.
FEATURES
• Extended Data Out Mode operation
(Fast Page Mode with Extended Data Out)
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• Part Identification
Operating
Voltage
Self-Refresh
Voltage(min)
Part No.
• RAS-only and Hidden refresh capability
• Self-refresh capability
K4E171613C-TL
K4E171613C-TN*
K4E171614C-TL
K4E171614C-TN*
3.0V
2.5V
2.5V
2.3V
• Self-refresh bump capability(3.0V product)
• LVTTL(3.0V/2.5V) compatible inputs and ouputs
• Early Write or output enable controlled write
• Available in plastic TSOP(ll) packages
• Single 3.0V+0.6V/-0.3V power supply (3.0V product)
• Single 2.5V±0.2V power supply (2.5V product)
* Extended temperature : -25°C to 85°C
• Active Power Dissipation
Unit : mW
Operation Voltage
Part No.
Speed
3.0V
324
-
2.5V
216
189
K4E171613C-TL(N)
K4E171614C-TL(N)
-60
-70
FUNCTIONAL BLOCK DIAGRAM
RAS
UCAS
LCAS
W
• Refresh Cycles
Part No.
Vcc
Vss
Control
Clocks
Refresh period
4K/128ms
VBB Generator
K4E171613C-TL(N)
K4E171614C-TL(N)
Lower
Data in
Buffer
DQ0
to
Row Decoder
Refresh Timer
Refresh Control
DQ7
Lower
Data out
Buffer
• Performance Range
Memory Array
1,048,576 x16
Cells
Speed
Part No.
tRAC tCAC
tRC
tHPC
OE
Refresh Counter
Row Address Buffer
Col. Address Buffer
Upper
Data in
Buffer
K4E171613C-TL(N)
K4E171614C-TL(N)
-60 60ns 17ns 104ns 25ns
-70 70ns 20ns 124ns 30ns
DQ8
to
DQ15
A0-A11
A0 - A7
Upper
Data out
Buffer
K4E171614C-TL(N)
Column Decoder
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.