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K3N4C1000D-TE100 PDF预览

K3N4C1000D-TE100

更新时间: 2024-11-20 18:43:15
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
3页 48K
描述
MASK ROM, 512KX16, 100ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44

K3N4C1000D-TE100 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2,
针数:44Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:100 ns
备用内存宽度:8JESD-30 代码:R-PDSO-G44
长度:18.41 mm内存密度:8388608 bit
内存集成电路类型:MASK ROM内存宽度:16
功能数量:1端子数量:44
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-20 °C组织:512KX16
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:10.16 mmBase Number Matches:1

K3N4C1000D-TE100 数据手册

 浏览型号K3N4C1000D-TE100的Datasheet PDF文件第2页浏览型号K3N4C1000D-TE100的Datasheet PDF文件第3页 
K3N4C1000D-TC(E)  
CMOS MASK ROM  
8M-Bit (1Mx8 /512Kx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
1,048,5762 x 8(byte mode)  
524,288 x 16(word mode)  
· Fast access time : 100ns(Max.)  
· Supply voltage : single +5V  
· Current consumption  
Operating : 50mA(Max.)  
Standby : 50mA(Max.)  
· Fully static operation  
The K3N4C1000D-TC(E) is a fully static mask programmable  
ROM fabricated using silicon gate CMOS process technology,  
and is organized either as 1,048,576 x8 bit(byte mode) or as  
524,288 x16 bit(word mode) depending on BHE voltage  
level.(See mode selection table)  
This device operates with a 5V single power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
· All inputs and outputs TTL compatible  
· Three state outputs  
· Package  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
-. K3N4C1000D-TC(E) : 44-TSOP2-400  
The K3N4C1000D-TC(E) is packaged in a 44-TSOP2.  
FUNCTIONAL BLOCK DIAGRAM  
PRODUCT INFORMATION  
Operating  
Temp Range  
Vcc Range  
(Typical)  
Speed  
(ns)  
Product  
A18  
X
MEMORY CELL  
MATRIX  
BUFFERS  
AND  
.
.
.
.
.
.
.
.
K3N4C1000D-TC  
K3N4C1000D-TE  
0°C~70°C  
5.0V  
100  
(524,288x16/  
1,048,576x8)  
-20°C~85°C  
DECODER  
PIN CONFIGURATION  
Y
SENSE AMP.  
BUFFERS  
AND  
DATA OUT  
BUFFERS  
DECODER  
A0  
N.C  
1
44 N.C  
A-1  
A18  
2
3
N.C  
A8  
43  
42  
41  
40  
39  
. . .  
A17  
A7  
4
A9  
CE  
A6  
A5  
A4  
A3  
A10  
A11  
5
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
6
OE  
7
38 A12  
37 A13  
BHE  
8
A14  
36  
A2  
A1  
9
A15  
35  
10  
11  
12  
13  
A0  
A16  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
TSOP2  
BHE  
VSS  
Pin Name  
A0 - A18  
Pin Function  
CE  
VSS  
Address Inputs  
Data Outputs  
OE 14  
Q15/A-1  
Q7  
Q0 - Q14  
Q0  
Q8  
Q1  
Q9  
15  
16  
17  
18  
Output 15(Word mode)/  
LSB Address(Byte mode)  
Q14  
Q6  
Q15 /A-1  
Q13  
Q5  
BHE  
CE  
Word/Byte selection  
Chip Enable  
Q2 19  
Q10 20  
Q12  
Q4  
OE  
Output Enable  
Power ( +5V)  
Ground  
Q3  
21  
Q11  
22  
VCC  
VCC  
VSS  
N.C  
No Connection  
K3N4C1000D-TC(E)  

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