Datasheet > ISPLSI6192DM-50LM

ISPLSI6192DM-50LM

更新时间： 2024-10-30 14:42:55

品牌	Logo	应用领域
莱迪思 - LATTICE		/
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59页	802K
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ispLSI 6192

High Density Programmable Logic with

Dedicated Memory and Register/Counter Modules

— 96 I/O Pins with Input Registers

— Security Cell Prevents Unauthorized Design Copy-

ing

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

Features

• A FAMILY OF HIGHLY INTEGRATED, CELL-BASED,

PROGRAMMABLE LOGIC DEVICES CONSISTING OF:

— Memory Module

— Register/Counter Module

— Programmable Logic Module

— fmax = 77 MHz Maximum Operating Frequency

— tpd = 15 ns Propagation Delay

— fcnt = 125 MHz Counter Frequency

— 50MHz FIFO Data Rate

— 159 User Logic/Memory/Register/Counter Pins

— 25000-Gate Overall Density

— 20ns Memory Access Time

— Electrically Erasable and Reprogrammable

— Unused Product Term Shutdown Saves Power

• MEMORY MODULE OPTIONS

— FIFO (6192FF), Single-Port RAM (6192SM) or Dual-

Port RAM (6192DM)

— Programmable Organizations:

• Single 256 x 18 or 512 x 9

• Dual 128 x 18 or 256 x 9 (6192SM)

— 31 Dedicated Data and Control Interface Pins

— Programmable Almost Empty and Almost Full Flags

(FIFO)

• IN-SYSTEM PROGRAMMABLE

— Supports ISP™ or ispJTAG™ Programming

— Change Logic and Interconnects in Seconds

— Reprogram Soldered Devices for Debugging

• IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

— Dedicated Arbitration/Busy Logic (Dual-Port RAM)

Functional Block Diagram

• REGISTER/COUNTER MODULE

— 8 Cascadable 16-Bit Functions

— 9 Programmable Modes Including Counter, Timer,

Shift Register and Register Options

Memory Module

Options:

• FIFO (6192FF)

• Single Port RAM (6192SM)

• Dual Port RAM (6192DM)

— 24 Dedicated Module Data and Control Pins Includ-

ing Terminal Count Flags

— Automatic Preload, Count Up/Down Options

Programmable Logic

• HIGH DENSITY PROGRAMMABLE LOGIC MODULE

— 8000-Gate General Purpose Programmable Logic

Block

— 192 General Purpose Logic Registers

— 24-Input, Twin Generic Logic Blocks (GLBs) Imple-

ment Any Registered or Combinatorial Functions

— High-Speed Global Interconnects

Module

Table 1. ispLSI 6192 Device Features

Module

General Programmable

Logic Module

Memory Module Options

Single-Port

SRAM

6192SM

Dual-Port

SRAM

6192DM

Programmable

/ Shift Register

Universal: Registered or

Combinatorial

FIFO

6192FF

Functions

Single: 512 x 9 or 256 x 18

Dual: 128 x 18 or 256 x 9 (6192SM Only)

Cascadeable 8 x 16 Bit

Words

Organization

(Programmable)

192 Macrocells

96 I/O / 5 Clocks /

2 Global Output Enables

18 I/O & 13 Control Pins

16 I/O & 8 Control Pins

External Interface

Performance

125MHz Counter

Frequency (Fcnt)

15ns Logic Delay (Tpd)

77MHz Frequency (Fmax)

20ns Memory Access Time (Tacc)

In-System Programmable

Programmability

Testability

IEEE 1149.1 Boundary Scan Test

208-Pin Metal Quad Flat Pack (MQFP)

Package

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com

May 1999

6192_05

12 3 4 5 6 7...59

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与ISPLSI6192DM-50LM相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI6192DM70LM	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI6192DM-70LM	LATTICE	获取价格	EE PLD, 18ns, 192-Cell, CMOS, PQFP208, MQFP-208
ISPLSI6192FF50LM	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI6192FF70LM	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI6192FF-70LM	LATTICE	获取价格	EE PLD, 18ns, 192-Cell, CMOS, PQFP208, MQFP-208
ISPLSI6192SM50LM	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI6192SM70LM	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI81080V-125LB272	LATTICE	获取价格	3.3V In-System Programmable SuperBIG⑩ High De
ISPLSI81080V-125LB492	LATTICE	获取价格	3.3V In-System Programmable SuperBIG⑩ High De
ISPLSI81080V-60LB272	LATTICE	获取价格	3.3V In-System Programmable SuperBIG⑩ High De

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