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ISPLSI81080V-125LB492 PDF预览

ISPLSI81080V-125LB492

更新时间: 2024-10-29 22:27:11
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
26页 334K
描述
3.3V In-System Programmable SuperBIG⑩ High Density PLD

ISPLSI81080V-125LB492 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA-492
针数:492Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.78其他特性:YES
最大时钟频率:125 MHz系统内可编程:YES
JESD-30 代码:S-PBGA-B492JESD-609代码:e0
JTAG BST:YES长度:35 mm
专用输入次数:I/O 线路数量:360
宏单元数:1080端子数量:492
最高工作温度:70 °C最低工作温度:
组织:0 DEDICATED INPUTS, 360 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA492,26X26,50封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
电源:2.5/3.3,3.3 V可编程逻辑类型:EE PLD
传播延迟:14.5 ns认证状态:Not Qualified
座面最大高度:3.25 mm子类别:Programmable Logic Devices
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:35 mm
Base Number Matches:1

ISPLSI81080V-125LB492 数据手册

 浏览型号ISPLSI81080V-125LB492的Datasheet PDF文件第2页浏览型号ISPLSI81080V-125LB492的Datasheet PDF文件第3页浏览型号ISPLSI81080V-125LB492的Datasheet PDF文件第4页浏览型号ISPLSI81080V-125LB492的Datasheet PDF文件第5页浏览型号ISPLSI81080V-125LB492的Datasheet PDF文件第6页浏览型号ISPLSI81080V-125LB492的Datasheet PDF文件第7页 
®
ispLSI 81080V  
3.3V In-System Programmable  
SuperBIG™ High Density PLD  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
Features  
• SuperBIG HIGH DENSITY IN-SYSTEM  
PROGRAMMABLE LOGIC  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
— 3.3V Power Supply  
— 60,000 PLD Gates/1080 Macrocells  
— 192-360 I/O Pins Supporting 3.3V/2.5V I/O  
— 1440 Registers  
— High-Speed Global and Big Fast Megablock (BFM)  
Interconnect  
— Wide 20-Macrocell Generic Logic Block (GLB) for  
High Performance  
— Wide Input Gating (44 Inputs per GLB) for Fast  
Counters, State Machines, Address Decoders, Etc.  
— PCB-Efficient Ball Grid Array (BGA) Package  
Options  
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY  
fmax = 125 MHz Maximum Operating Frequency  
tpd = 8.5 ns Propagation Delay  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
Functional Block Diagram  
12  
12  
12  
12  
12  
I/O  
12  
I/O  
I/O  
I/O  
I/O  
I/O  
12  
I/O  
12  
I/O  
Big Fast Megablock 0  
Big Fast Megablock 1  
Big Fast Megablock 2  
Big Fast Megablock 3  
12  
I/O  
12  
I/O  
12  
I/O  
12  
I/O  
— Programmable Speed/Power Logic Path  
Optimization  
• IN-SYSTEM PROGRAMMABLE  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
12  
I/O  
12  
I/O  
— Reprogram Soldered Devices for Faster Debugging  
12  
I/O  
12  
I/O  
Big Fast Megablock 4  
Global Routing Plane  
Big Fast Megablock 5  
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND  
3.3V IN-SYSTEM PROGRAMMABLE  
12  
I/O  
12  
I/O  
• ARCHITECTURE FEATURES  
— Enhanced Pin-Locking Architecture, Symmetrical  
Generic Logic Blocks Connected by Hierarchical  
Big Fast Megablock and Global Routing Planes  
— Product Term Sharing Array Supports up to 28  
Product Terms per Macrocell Output  
— Macrocells Support Concurrent Combinatorial and  
Registered Functions  
— Embedded Tristate Bus Can Be Used as an Internal  
Tristate Bus or as an Extension of an External  
Tristate Bus  
12  
I/O  
12  
I/O  
Big Fast Megablock 6  
Big Fast Megablock 7  
Big Fast Megablock 8  
12  
I/O  
12  
I/O  
12  
I/O  
12  
I/O  
— Macrocell and I/O Registers Feature Multiple Control  
Options, Including Set, Reset and Clock Enable  
— I/O Pins Support Programmable Bus Hold, Pull-Up,  
Open-Drain and Slew Rate Options  
Boundary  
Scan  
12  
I/O  
12  
I/O  
12  
I/O  
12  
I/O  
12  
I/O  
12  
I/O  
81080v block  
— Separate VCCIO Power Supply to Support 3.3V or  
2.5V Input/Output Logic Levels  
ispLSI 8000V Family Description  
— I/O Cell Register Programmable as Input Register for  
Fast Setup Time or Output Register for Fast Clock to  
Output Time  
The ispLSI 8000V Family of Register-Intensive, 3.3V  
SuperBIG In-System Programmable Logic Devices is  
based on Big Fast Megablocks of 120 registered macro-  
cells and a Global Routing Plane (GRP) structure  
Copyright©2000LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
July 2000  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
81080v_03  
1

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