Datasheet > ISPLSI8840V-125LB272

ISPLSI8840V-125LB272

更新时间： 2024-10-29 23:59:51

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ispLSI 8840V

3.3V In-System Programmable

SuperBIG™ High Density PLD

Features

Functional Block Diagram

• SuperBIG HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

I/O

— 3.3V Power Supply

— 45,000 PLD Gates/840 Macrocells

— 192-312 I/O Pins Supporting 3.3V/2.5V I/O

— 1152 Registers

— High-Speed Global and Big Fast Megablock (BFM)

Interconnect

I/O

Big Fast Megablock 0

Big Fast Megablock 1

I/O

— Wide 20-Macrocell Generic Logic Block (GLB) for

High Performance

I/O

— Wide Input Gating (44 Inputs per GLB) for Fast

Counters, State Machines, Address Decoders, Etc.

— PCB-Efficient Ball Grid Array (BGA) Package

Options

Big Fast Megablock 2

Global Routing Plane

Big Fast Megablock 3

I/O

• HIGH-PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 125 MHz Maximum Operating Frequency

— tpd = 8.5 ns Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

I/O

Big Fast Megablock 4

Big Fast Megablock 5

Big Fast Megablock 6

I/O

— Programmable Speed/Power Logic Path

Optimization

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

I/O

— Reprogram Soldered Devices for Faster Debugging

Boundary

Scan

I/O

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

3.3V IN-SYSTEM PROGRAMMABLE

8840v block

• ARCHITECTURE FEATURES

ispLSI 8000V Family Description

— Enhanced Pin-Locking Architecture, Symmetrical

Generic Logic Blocks Connected by Hierarchical

Big Fast Megablock and Global Routing Planes

— Product Term Sharing Array Supports up to 28

Product Terms per Macrocell Output

— Macrocells Support Concurrent Combinatorial and

Registered Functions

— Embedded Tristate Bus Can Be Used as an Internal

Tristate Bus or as an Extension of an External

Tristate Bus

— Macrocell and I/O Registers Feature Multiple Control

Options, Including Set, Reset and Clock Enable

— I/O Pins Support Programmable Bus Hold, Pull-Up,

Open-Drain and Slew Rate Options

— Separate VCCIO Power Supply to Support 3.3V or

2.5V Input/Output Logic Levels

— I/O Cell Register Programmable as Input Register for

Fast Setup Time or Output Register for Fast Clock to

Output Time

The ispLSI 8000V Family of Register-Intensive, 3.3V

SuperBIG In-System Programmable Logic Devices is

based on Big Fast Megablocks of 120 registered macro-

cells and a Global Routing Plane (GRP) structure

interconnecting the Big Fast Megablocks. Each Big Fast

Megablock contains 120 registered macrocells arranged

in six groups of 20, a group of 20 being referred to as a

Generic Logic Block, or GLB. Within the Big Fast

Megablock, a Big Fast Megablock Routing Pool (BRP)

interconnects the six GLBs to each other and to 24 Big

Fast Megablock I/O cells with optional I/O registers. The

Global Routing Plane which interconnects the Big Fast

Megablocks has additional global I/Os with optional I/O

registers. The 192-I/O version contains 72 Big Fast

Megablock I/Os and 120 global I/Os, while the 312-I/O

version contains 168 Big Fast Megablock I/Os and 144

global I/Os.

to change without notice.

January 2002

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

8840v_04

12 3 4 5 6 7...26

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与ISPLSI8840V-125LB272相关器件

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ISPLSI8840V-125LB492	ETC	获取价格
ISPLSI8840V-60LB272	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI8840V-60LB492	ETC	获取价格
ISPLSI8840V-90LB272	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI8840V-90LB492	ETC	获取价格
ISPMACH4000B	LATTICE	获取价格	3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
ISPMACH4000C	LATTICE	获取价格	3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
ISPMACH4000V	LATTICE	获取价格	3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
ISPMACH4000ZE	LATTICE	获取价格	1.8V In-System Programmable Ultra Low Power PLDs
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