®
ispLSI 5512VE
In-System Programmable
3.3V SuperWIDE™ High Density PLD
Features
Functional Block Diagram
• Second Generation SuperWIDE HIGH DENSITY
IN-SYSTEM PROGRAMMABLE LOGIC DEVICE
— 3.3V Power Supply
Input Bus
Input Bus
Input Bus
Input Bus
Boundary
Scan
Interface
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
— User Selectable 3.3V/2.5V I/O
— 24000 PLD Gates / 512 Macrocells
— Up to 256 I/O Pins
— 512 Registers
— High-Speed Global Interconnect
— SuperWIDE Generic Logic Block (32 Macrocells) for
Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package Options
— Interfaces with Standard 5V TTL Devices
Global Routing Pool
(GRP)
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 155 MHz Maximum Operating Frequency
— tpd = 6.5 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
— Programmable Speed/Power Logic Path Optimization
Input Bus
Input Bus
Input Bus
Input Bus
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
ispLSI 5000VE Description
The ispLSI 5000VE Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with Single-
Level Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports
up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Macrocell Registers Feature Multiple Control
Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell
Product Term Clocks
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are pro-
vided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and three extra control product terms. The GLB has 68
inputs from the Global Routing Pool which are available
in both true and complement form for every product term.
The 160 product terms are grouped in 32 sets of five and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 35 product terms for
a single function. Alternatively, the PTSA can be by-
passed for functions of five product terms or less. The
three extra product terms are used for shared controls:
reset, clock, clock enable and output enable.
— Programmable I/O Supports Programmable Bus
Hold, Pull-up, Open Drain and Slew Rate Options
— Four Global Product Term Output Enables, Two
Global OE Pins and One Product Term OE per
Macrocell
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP™ DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER
— PC and UNIX Platforms
Copyright©2001LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
April 2001
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