Datasheet > ISPLSI3256E70LB320

ISPLSI3256E70LB320

更新时间： 2024-10-29 03:05:51

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
15页	246K
描述
In-System Programmable High Density PLD

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ispLSI 3256E

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 256 I/O Pins

— 12000 PLD Gates

ORP

Boundary

Scan

H3 H2 H1 H0

G3 G2 G1 G0

— 512 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Array

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 100 MHz Maximum Operating Frequency

— tpd = 10 ns Propagation Delay

Twin

GLB

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

Array

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

Global Routing Pool

• IN-SYSTEM PROGRAMMABLE

— 5V In-System Programmable (ISP™) using Lattice

ISP or Boundary Scan Test (IEEE 1149.1) Protocol

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

C0 C1 C2 C3

ORP ORP

D1 D2

ORP

— Reprogram Soldered Devices for Faster Debugging

0139A/3256E

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

Description

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

The ispLSI 3256E is a High Density Programmable Logic

Device containing 512 Registers, 256 Universal I/O pins,

five Dedicated Clock Input Pins, 16 Output Routing Pools

(ORP) and a Global Routing Pool (GRP) which allows

complete inter-connectivity between all of these ele-

ments. The ispLSI 3256E features 5V in-system

programmability and in-system diagnostic capabilities.

The ispLSI 3256E offers non-volatile reprogrammability

of the logic, as well as the interconnect to provide truly

reconfigurable systems.

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

mize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

The basic unit of logic on the ispLSI 3256E device is the

TwinGenericLogicBlock(TwinGLB)labelledA0,A1...H3.

There are a total of 32 Twin GLBs in the ispLSI 3256E

device. Each Twin GLB has 24 inputs, a programmable

AND array and two OR/Exclusive-OR Arrays and eight

outputs which can be configured to be either combinato-

rial or registered. All Twin GLB inputs come from the

GRP.

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

March 2007

3256e_09

12 3 4 5 6 7...15

中文翻译

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与ISPLSI3256E70LB320相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI3256E-70LB320	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI3256E-70LM	LATTICE	获取价格	EE PLD, 18ns, 256-Cell, CMOS, PQFP304, MQFP-304
ISPLSI3256E70LQ	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI3256E-70LQ	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI3256E70LQA	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI3256E-70LQA	LATTICE	获取价格	EE PLD, 15ns, 256-Cell, CMOS, PQFP304, PLASTIC, QFP-304
ISPLSI3320-100LB320	LATTICE	获取价格	EE PLD, 13ns, 320-Cell, CMOS, PBGA320, BGA-320
ISPLSI3320-100LM	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI3320-100LQ	LATTICE	获取价格	EE PLD, 13ns, 320-Cell, CMOS, PQFP208, HEAT SPREADER, PLASTIC, QFP-208
ISPLSI3320-70LB320	LATTICE	获取价格	EE PLD, 18ns, 320-Cell, CMOS, PBGA320, BGA-320

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