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ISPLSI5128VE-100LT128I

更新时间： 2024-10-28 21:54:19

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
21页	211K
描述
In-System Programmable 3.3V SuperWIDE High Density PLD

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ispLSI 5128VE

In-System Programmable

3.3V SuperWIDE™ High Density PLD

Features

Functional Block Diagram

• Second Generation SuperWIDE HIGH DENSITY

IN-SYSTEM PROGRAMMABLE LOGIC DEVICE

— 3.3V Power Supply

Input Bus

Boundary

Scan

Interface

Generic

Logic Block

— User Selectable 3.3V/2.5V I/O

— 6000 PLD Gates / 128 Macrocells

— 96 I/O Pins Available

— 128 Registers

— High-Speed Global Interconnect

— SuperWIDE Generic Logic Block (32 Macrocells) for

Optimum Performance

— SuperWIDE Input Gating (68 Inputs) for Fast

Counters, State Machines, Address Decoders, etc.

Global Routing Pool

(GRP)

—

Interfaces with Standard 5V TTL Devices

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 180 MHz Maximum Operating Frequency

— tpd = 5.0 ns Propagation Delay

— TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path Optimization

Generic

Logic Block

Input Bus

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

ispLSI 5000VE Description

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

3.3V IN-SYSTEM PROGRAMMABLE

The ispLSI 5000VE Family of In-System Programmable

High Density Logic Devices is based on Generic Logic

Blocks (GLBs) of 32 registered macrocells and a single

Global Routing Pool (GRP) structure interconnecting the

GLBs.

• ARCHITECTURE FEATURES

— Enhanced Pin-Locking Architecture with Single-

Level Global Routing Pool and SuperWIDE GLBs

— Wrap Around Product Term Sharing Array Supports

up to 35 Product Terms Per Macrocell

Outputs from the GLBs drive the Global Routing Pool

(GRP) between the GLBs. Switching resources are pro-

vided to allow signals in the Global Routing Pool to drive

any or all the GLBs in the device. This mechanism allows

fast, efficient connections across the entire device.

— Macrocells Support Concurrent Combinatorial and

Registered Functions

— Macrocell Registers Feature Multiple Control

Options Including Set, Reset and Clock Enable

— Four Dedicated Clock Input Pins Plus Macrocell

Product Term Clocks

— Programmable I/O Supports Programmable Bus

Hold, Pull-up, Open Drain and Slew Rate Options

— Four Global Product Term Output Enables, Two

Global OE Pins and One Product Term OE per

Macrocell

Each GLB contains 32 macrocells and a fully populated,

programmable AND-array with 160 logic product terms

and three extra control product terms. The GLB has 68

inputs from the Global Routing Pool which are available

in both true and complement form for every product term.

The 160 product terms are grouped in 32 sets of five and

sent into a Product Term Sharing Array (PTSA) which

allows sharing up to a maximum of 35 product terms for

a single function. Alternatively, the PTSA can be by-

passed for functions of five product terms or less. The

three extra product terms are used for shared controls:

reset, clock, clock enable and output enable.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

January 2002

5128ve_05

12 3 4 5 6 7...21

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与ISPLSI5128VE-100LT128I相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI5128VE-125LT128	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE High Density PLD
ISPLSI5128VE-125LT128I	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE High Density PLD
ISPLSI5128VE-180LT128	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE High Density PLD
ISPLSI5128VE-180LT128I	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE High Density PLD
ISPLSI5128VE-80LT128	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE High Density PLD
ISPLSI5128VE-80LT128I	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE High Density PLD
ISPLSI5256V-100LB	LATTICE	获取价格	EE PLD, 10ns, CMOS, PBGA272, BGA-272
ISPLSI5256V-100LB208	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE? High Density PLD
ISPLSI5256V-100LB272	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE? High Density PLD
ISPLSI5256V-100LQ208	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE? High Density PLD

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