Datasheet > ISPLSI3320-70LM

ISPLSI3320-70LM

更新时间： 2024-10-28 23:59:51

品牌	Logo	应用领域
其他 - ETC		可编程逻辑输入元件时钟
页数	文件大小	规格书
16页	195K
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ISPLSI3320-70LM 数据手册

ispLSI 3320

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 160 I/O Pins

— 14000 PLD Gates

Output Routing Pool (ORP)

G3 G2 G1 G0

Output Routing Pool (ORP)

Boundary

Scan

— 480 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Array

Twin

GLB

• HIGH-PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 100 MHz Maximum Operating Frequency

— tpd = 10 ns Propagation Delay

Array

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• ispLSI FEATURES:

— 5V In-System Programmable (ISP™) Using Lattice

ISP or Boundary Scan Test (IEEE 1149.1) Protocol

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

Global Routing Pool

(GRP)

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

Output Routing Pool (ORP)

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

0139/3320

Description

The ispLSI 3320 is a High-Density Programmable Logic

Device containing 480 Registers, 160 Universal I/O pins,

five Dedicated Clock Input Pins, ten Output Routing

Pools (ORP) and a Global Routing Pool (GRP) which

allows complete inter-connectivity between all of these

elements. The ispLSI 3320 features 5V in-system pro-

grammability and in-system diagnostic capabilities. The

ispLSI 3320 offers non-volatile reprogrammability of the

logic, as well as the interconnect to provide truly

reconfigurable systems.

— Enhanced Pin Locking Capability

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

— Pin Compatible with ispLSI 3160

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

The basic unit of logic on the ispLSI 3320 device is the

TwinGenericLogicBlock(TwinGLB)labelledA0,A1...J3.

There are a total of 40 of these Twin GLBs in the ispLSI

3320 device. Each Twin GLB has 24 inputs, a program-

mable AND array and two OR/Exclusive-OR Arrays, and

eight outputs which can be configured to be either com-

binatorial or registered. All Twin GLB inputs come from

the GRP.

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

May 1999

3320_06

12 3 4 5 6 7...16

中文翻译

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与ISPLSI3320-70LM相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI3320-70LQ	LATTICE	获取价格	EE PLD, 18ns, 320-Cell, CMOS, PQFP208, HEAT SPREADER, PLASTIC, QFP-208
ISPLSI3448	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI3448-70LB	LATTICE	获取价格	EE PLD, 18ns, CMOS, PBGA432, 39.90 X 39.90 MM, BGA-432
ISPLSI3448-70LB432	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI3448-90LB	LATTICE	获取价格	EE PLD, 15ns, CMOS, PBGA432, 39.90 X 39.90 MM, BGA-432
ISPLSI3448-90LB432	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI5128VE	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE High Density PLD
ISPLSI5128VE-100LT128	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE High Density PLD
ISPLSI5128VE-100LT128I	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE High Density PLD
ISPLSI5128VE-125LT128	LATTICE	获取价格	In-System Programmable 3.3V SuperWIDE High Density PLD

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