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ISPLSI3448-90LB432 PDF预览

ISPLSI3448-90LB432

更新时间： 2024-10-29 05:11:51
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
14页 173K
描述
In-System Programmable High Density PLD

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ISPLSI3448-90LB432 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：LBGA, BGA432,31X31,50
针数：432Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.92其他特性：YES
最大时钟频率：62.5 MHz系统内可编程：YES
JESD-30 代码：S-PBGA-B432JESD-609代码：e0
JTAG BST：YES长度：40 mm
湿度敏感等级：3专用输入次数：
I/O 线路数量：224宏单元数：448
端子数量：432最高工作温度：70 °C
最低工作温度：组织：0 DEDICATED INPUTS, 224 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA432,31X31,50
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE
电源：5 V可编程逻辑类型：EE PLD
传播延迟：15 ns认证状态：Not Qualified
座面最大高度：1.7 mm子类别：Programmable Logic Devices
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
宽度：40 mmBase Number Matches：1

ISPLSI3448-90LB432 数据手册

 浏览型号ISPLSI3448-90LB432的Datasheet PDF文件第2页浏览型号ISPLSI3448-90LB432的Datasheet PDF文件第3页浏览型号ISPLSI3448-90LB432的Datasheet PDF文件第4页浏览型号ISPLSI3448-90LB432的Datasheet PDF文件第5页浏览型号ISPLSI3448-90LB432的Datasheet PDF文件第6页浏览型号ISPLSI3448-90LB432的Datasheet PDF文件第7页 
®
ispLSI 3448  
In-System Programmable High Density PLD  
Features  
Functional Block Diagram  
• HIGH-DENSITY PROGRAMMABLE LOGIC  
— 224 I/O  
— 20000 PLD Gates  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
Boundary  
Scan  
...  
J3  
J2  
J1  
J0  
H3  
H2  
H1  
H0  
— 672 Registers  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
K0  
K1  
K2  
G3  
G2  
G1  
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
OR  
Array  
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 90 MHz Maximum Operating Frequency  
— tpd = 12 ns Propagation Delay  
Twin  
GLB  
K3  
G0  
D
D
D
D
OR  
— TTL Compatible Inputs and Outputs  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
Array  
N0  
N1  
N2  
D3  
D2  
D1  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
Global Routing Pool  
(GRP)  
• ispLSI FEATURES:  
— 5V In-System Programmable (ISP™) Using Lattice  
ISP or Boundary Scan Test (IEEE 1149.1) Protocol  
— Increased Manufacturing Yields, Reduced Time-to-  
Market, and Improved Product Quality  
N3  
D0  
A0  
A1  
A2  
A3  
C0  
C1  
C2  
C3  
— Reprogram Soldered Devices for Faster Debugging  
...  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE  
0139/3448  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
— Enhanced Pin Locking Capability  
— Five Dedicated Clock Inputs  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to Mini-  
mize Switching Noise  
Description  
The ispLSI 3448 is a High-Density Programmable Logic  
Devicecontaining672Registers, 224UniversalI/Os, five  
Dedicated Clock Inputs, 14 Output Routing Pools (ORP)  
and a Global Routing Pool (GRP) which allows complete  
inter-connectivity between all of these elements. The  
ispLSI 3448 features 5V in-system programmability and  
in-systemdiagnosticcapabilities. TheispLSI3448offers  
non-volatile reprogrammabilityofthelogic, aswellasthe  
interconnect to provide truly reconfigurable systems.  
— Flexible I/O Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
The basic unit of logic on the ispLSI 3448 device is the  
TwinGenericLogicBlock(TwinGLB)labelledA0,A1...N3.  
There are a total of 56 of these Twin GLBs in the ispLSI  
3448 device. Each Twin GLB has 24 inputs, a program-  
mable AND array and two OR/Exclusive-OR Arrays, and  
eight outputs which can be configured to be either com-  
binatorial or registered. All Twin GLB inputs come from  
the GRP.  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
Copyright©2000LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
February 2000  
3448_06  
1
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