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ISPLSI5256V-125LB208 PDF预览

ISPLSI5256V-125LB208

更新时间： 2024-10-29 11:13:31
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
25页 306K
描述
In-System Programmable 3.3V SuperWIDE? High Density PLD

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ISPLSI5256V-125LB208 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：1 MM PITCH, FBGA-208
针数：208Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.91其他特性：YES
最大时钟频率：87 MHz系统内可编程：YES
JESD-30 代码：S-PBGA-B208JTAG BST：YES
长度：17 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：144
宏单元数：256端子数量：208
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 144 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA208,16X16,40封装形状：SQUARE
封装形式：GRID ARRAY电源：2.5/3.3,3.3 V
可编程逻辑类型：EE PLD传播延迟：9.5 ns
认证状态：Not Qualified座面最大高度：2.1 mm
子类别：Programmable Logic Devices最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
宽度：17 mmBase Number Matches：1

ISPLSI5256V-125LB208 数据手册

 浏览型号ISPLSI5256V-125LB208的Datasheet PDF文件第2页浏览型号ISPLSI5256V-125LB208的Datasheet PDF文件第3页浏览型号ISPLSI5256V-125LB208的Datasheet PDF文件第4页浏览型号ISPLSI5256V-125LB208的Datasheet PDF文件第5页浏览型号ISPLSI5256V-125LB208的Datasheet PDF文件第6页浏览型号ISPLSI5256V-125LB208的Datasheet PDF文件第7页 
®
ispLSI 5256V  
In-System Programmable  
3.3V SuperWIDE™ High Density PLD  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
Features  
• SuperWIDE HIGH-DENSITY IN-SYSTEM  
PROGRAMMABLE LOGIC  
— 3.3V Power Supply  
Functional Block Diagram  
— User Selectable 3.3V/2.5V I/O  
— 12000 PLD Gates / 256 Macrocells  
— Up to 192 I/O Pins  
Input Bus  
Input Bus  
Boundary  
Scan  
Interface  
— 256 Registers  
Generic  
Logic Block  
Generic  
Logic Block  
— High-Speed Global Interconnect  
— SuperWIDE 32 Generic Logic Block (GLB) Size for  
Optimum Performance  
— SuperWIDE Input Gating (68 Inputs) for Fast  
Counters, State Machines, Address Decoders, etc.  
— PCB Efficient Ball Grid Array (BGA) Package  
Options  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 125 MHz Maximum Operating Frequency  
— tpd = 7.5 ns Propagation Delay  
— TTL/3.3V/2.5V Compatible Input Thresholds and  
Output Levels  
Global Routing Pool  
(GRP)  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
— Programmable Speed/Power Logic Path  
Optimization  
• IN-SYSTEM PROGRAMMABLE  
— Increased Manufacturing Yields, Reduced Time-to-  
Market, and Improved Product Quality  
Generic  
Logic Block  
Generic  
Logic Block  
Input Bus  
Input Bus  
— Reprogram Soldered Devices for Faster Debugging  
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND  
3.3V IN-SYSTEM PROGRAMMABLE  
ispLSI 5000V Description  
• ARCHITECTURE FEATURES  
The ispLSI 5000V Family of In-System Programmable  
High Density Logic Devices is based on Generic Logic  
Blocks (GLBs) of 32 registered macrocells and a single  
Global Routing Pool (GRP) structure interconnecting the  
GLBs.  
— Enhanced Pin-Locking Architecture with Single-  
Level Global Routing Pool and SuperWide GLBs  
— Wrap Around Product Term Sharing Array Supports  
up to 35 Product Terms Per Macrocell  
— Macrocells Support Concurrent Combinatorial and  
Registered Functions  
— Macrocell Registers Feature Multiple Control  
Options Including Set, Reset and Clock Enable  
— Four Dedicated Clock Input Pins Plus Macrocell  
Product Term Clocks  
— Slew and Skew Programmable I/O (SASPI/O™)  
Supports Programmable Bus Hold, Pull-up, Open  
Drain and Slew and Skew Rate Options  
Outputs from the GLBs drive the Global Routing Pool  
(GRP) between the GLBs. Switching resources are pro-  
vided to allow signals in the Global Routing Pool to drive  
any or all the GLBs in the device. This mechanism allows  
fast, efficient connections across the entire device.  
Each GLB contains 32 macrocells and a fully populated,  
programmable AND-array with 160 logic product terms  
and5extracontrolproductterms. TheGLBhas68inputs  
from the Global Routing Pool which are available in both  
true and complement form for every product term. The  
160 product terms are grouped in 32 sets of five and sent  
into a Product Term Sharing Array (PTSA) which allows  
— Six Global Output Enable Terms, Two Global OE  
Pins and One Product Term OE per Macrocell  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
Copyright©1999LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
May 1999  
5256v_03  
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ISPLSI5256V-125LB208 替代型号

型号 品牌 替代类型 描述 数据表
ISPLSI5256V-100LB208 LATTICE

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