Datasheet > ISPLSI3256E-70LM

ISPLSI3256E-70LM

更新时间： 2024-10-29 20:22:51

品牌	Logo	应用领域
莱迪思 - LATTICE		时钟输入元件可编程逻辑
页数	文件大小	规格书
15页	218K
描述
EE PLD, 18ns, 256-Cell, CMOS, PQFP304, MQFP-304

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技术参数
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ISPLSI3256E-70LM 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	MQFP-304
针数：	304	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.84	Is Samacsys：	N
其他特性：	SYNCHRONOUS & ASYNCHRONOUS CLOCKS; 32 GLBS	最大时钟频率：	50 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQFP-G304
JESD-609代码：	e0	JTAG BST：	YES
长度：	39.7 mm	专用输入次数：
I/O 线路数量：	256	宏单元数：	256
端子数量：	304	最高工作温度：	70 °C
最低工作温度：		组织：	0 DEDICATED INPUTS, 256 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	FQFP	封装等效代码：	QFP304,1.7SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	18 ns	认证状态：	Not Qualified
座面最大高度：	4.55 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	39.7 mm	Base Number Matches：	1

ISPLSI3256E-70LM 数据手册

ispLSI 3256E

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 256 I/O Pins

— 12000 PLD Gates

ORP

Boundary

Scan

H3 H2 H1 H0

G3 G2 G1 G0

— 512 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Array

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 100 MHz Maximum Operating Frequency

— tpd = 10 ns Propagation Delay

Twin

GLB

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

Array

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

Global Routing Pool

• IN-SYSTEM PROGRAMMABLE

— 5V In-System Programmable (ISP™) using Lattice

ISP or Boundary Scan Test (IEEE 1149.1) Protocol

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

C0 C1 C2 C3

ORP ORP

D1 D2

ORP

— Reprogram Soldered Devices for Faster Debugging

0139A/3256E

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

Description

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

The ispLSI 3256E is a High Density Programmable Logic

Device containing 512 Registers, 256 Universal I/O pins,

five Dedicated Clock Input Pins, 16 Output Routing Pools

(ORP) and a Global Routing Pool (GRP) which allows

complete inter-connectivity between all of these ele-

ments. The ispLSI 3256E features 5V in-system

programmability and in-system diagnostic capabilities.

The ispLSI 3256E offers non-volatile reprogrammability

of the logic, as well as the interconnect to provide truly

reconfigurable systems.

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

mize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispEXPERT™ – LOGIC COMPILER AND COMPLETE

ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS

THROUGH IN-SYSTEM PROGRAMMING

The basic unit of logic on the ispLSI 3256E device is the

TwinGenericLogicBlock(TwinGLB)labelledA0,A1...H3.

There are a total of 32 Twin GLBs in the ispLSI 3256E

device. Each Twin GLB has 24 inputs, a programmable

AND array and two OR/Exclusive-OR Arrays and eight

outputs which can be configured to be either combinato-

rial or registered. All Twin GLB inputs come from the

GRP.

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8037; http://www.latticesemi.com

May 1999

3256e_07

12 3 4 5 6 7...15

中文翻译

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与ISPLSI3256E-70LM相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI3256E70LQ	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI3256E-70LQ	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI3256E70LQA	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI3256E-70LQA	LATTICE	获取价格	EE PLD, 15ns, 256-Cell, CMOS, PQFP304, PLASTIC, QFP-304
ISPLSI3320-100LB320	LATTICE	获取价格	EE PLD, 13ns, 320-Cell, CMOS, PBGA320, BGA-320
ISPLSI3320-100LM	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI3320-100LQ	LATTICE	获取价格	EE PLD, 13ns, 320-Cell, CMOS, PQFP208, HEAT SPREADER, PLASTIC, QFP-208
ISPLSI3320-70LB320	LATTICE	获取价格	EE PLD, 18ns, 320-Cell, CMOS, PBGA320, BGA-320
ISPLSI3320-70LM	ETC	获取价格
ISPLSI3320-70LQ	LATTICE	获取价格	EE PLD, 18ns, 320-Cell, CMOS, PQFP208, HEAT SPREADER, PLASTIC, QFP-208

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