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ISPLSI2128A-100LT176 PDF预览

ISPLSI2128A-100LT176

更新时间: 2024-10-28 23:59:51
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ISPLSI2128A-100LT176 数据手册

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®
ispLSI 2128/A  
In-System Programmable High Density PLD  
Features  
Functional Block Diagram  
• ENHANCEMENTS  
Output Routing Pool (ORP)  
D7 D6  
D5  
D4  
Output Routing Pool (ORP)  
D2  
D1  
D0  
— ispLSI 2128A is Fully Form and Function Compatible  
to the ispLSI 2128, with Identical Timing  
Specifcations and Packaging  
D3  
A0  
A1  
C7  
C6  
— ispLSI 2128A is Built on an Advanced 0.35 Micron  
E2CMOS® Technology  
• HIGH DENSITY PROGRAMMABLE LOGIC  
D
Q
Q
Q
Q
A2  
A3  
C5  
C4  
— 6000 PLD Gates  
— 128 I/O Pins, Eight Dedicated Inputs  
— 128 Registers  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
D
D
D
Logic  
Array  
A4  
A5  
C3  
C2  
GLB  
A6  
A7  
C1  
C0  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
Global Routing Pool (GRP)  
fmax = 100 MHz Maximum Operating Frequency  
tpd = 10 ns Propagation Delay  
B0  
B1  
B2  
B3  
B5  
B6  
B7  
B4  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
— TTL Compatible Inputs and Outputs  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
0139(9A)/2128  
Description  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
The ispLSI 2128 and 2128A are High Density Program-  
mableLogicDevices.Thedevicescontains128Registers,  
128 Universal I/O pins, eight Dedicated Input pins, three  
Dedicated Clock Input pins, two dedicated Global OE  
input pins and a Global Routing Pool (GRP). The GRP  
provides complete interconnectivity between all of these  
elements. The ispLSI 2128 and 2128A feature 5V in-  
system programmability and in-system diagnostic  
capabilities. The ispLSI 2128 and 2128A offer non-  
volatile reprogrammability of the logic, as well as the  
interconnect to provide truly reconfigurable systems.  
• IN-SYSTEM PROGRAMMABLE  
— In-System Programmable (ISP™) 5V Only  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to  
Minimize Switching Noise  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
The basic unit of logic on these devices is the Generic  
Logic Block (GLB). The GLBs are labeled A0, A1 .. D7  
(Figure1). Thereareatotalof32GLBsintheispLSI2128  
and 2128A devices. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
Copyright©2002LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
January 2002  
2128_09  
1

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