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ISPLSI2128E-100LT176 PDF预览

ISPLSI2128E-100LT176

更新时间： 2024-10-28 22:11:19
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
11页 144K
描述
In-System Programmable SuperFAST⑩ High Density PLD

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ISPLSI2128E-100LT176 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-176针数：176
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.76
Is Samacsys：N其他特性：IN-SYSTEM PROGRAMMABLE
最大时钟频率：77 MHz系统内可编程：YES
JESD-30 代码：S-PQFP-G176JESD-609代码：e0
JTAG BST：NO长度：24 mm
湿度敏感等级：3专用输入次数：4
I/O 线路数量：128宏单元数：128
端子数量：176最高工作温度：70 °C
最低工作温度：组织：4 DEDICATED INPUTS, 128 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP176,1.0SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：225电源：3.3/5,5 V
可编程逻辑类型：EE PLD传播延迟：13 ns
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Programmable Logic Devices最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：24 mmBase Number Matches：1

ISPLSI2128E-100LT176 数据手册

 浏览型号ISPLSI2128E-100LT176的Datasheet PDF文件第2页浏览型号ISPLSI2128E-100LT176的Datasheet PDF文件第3页浏览型号ISPLSI2128E-100LT176的Datasheet PDF文件第4页浏览型号ISPLSI2128E-100LT176的Datasheet PDF文件第5页浏览型号ISPLSI2128E-100LT176的Datasheet PDF文件第6页浏览型号ISPLSI2128E-100LT176的Datasheet PDF文件第7页 
®
ispLSI 2128E  
In-System Programmable  
SuperFAST™ High Density PLD  
Features  
Functional Block Diagram  
• SUPERFAST HIGH DENSITY IN-SYSTEM  
PROGRAMMABLE LOGIC  
Output Routing Pool (ORP)  
D7 D6  
D5  
D4  
Output Routing Pool (ORP)  
D2  
D1  
D0  
D3  
— 6000 PLD Gates  
— 128 I/O Pins, Eight Dedicated Inputs  
— 128 Registers  
A0  
A1  
C7  
C6  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
— 100% Functional/JEDEC Upward Compatible with  
ispLSI 2128 Devices  
D
Q
Q
Q
Q
A2  
A3  
C5  
C4  
D
D
D
Logic  
Array  
A4  
A5  
C3  
C2  
GLB  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 180 MHz Maximum Operating Frequency  
— tpd = 5.0 ns Propagation Delay  
— TTL Compatible Inputs and Outputs  
— 5V Programmable Logic Core  
A6  
A7  
C1  
C0  
Global Routing Pool (GRP)  
— ispJTAG™ In-System Programmable via IEEE 1149.1  
(JTAG) Test Access Port  
B0  
B1  
B2  
B3  
B5  
B6  
B7  
B4  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
— User-Selectable 3.3V or 5V I/O Supports Mixed-  
Voltage Systems  
0139(9A)/2128  
— PCI Compatible Outputs  
— Open-Drain Output Option  
Description  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
— Unused Product Term Shutdown Saves Power  
The ispLSI 2128E is a High Density Programmable Logic  
Device. The device contains 128 Registers, 128 Univer-  
sal I/O pins, eight Dedicated Input pins, three Dedicated  
Clock Input pins, two dedicated Global OE input pins and  
a Global Routing Pool (GRP). The GRP provides com-  
plete interconnectivity between all of these elements.  
The ispLSI 2128E features 5V in-system programmabil-  
ity and in-system diagnostic capabilities. The ispLSI  
2128E offers non-volatile reprogrammability of all logic,  
as well as the interconnect to provide truly reconfigurable  
systems.  
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to  
Minimize Switching Noise  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
The basic unit of logic on the ispLSI 2128E device is the  
Generic Logic Block (GLB). The GLBs are labeled A0, A1  
.. D7 (see Figure 1). There are a total of 32 GLBs in the  
ispLSI 2128E device. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or  
registered.Inputs to the GLB come from the GRP and  
dedicated inputs. All of the GLB outputs are brought back  
into the GRP so that they can be connected to the inputs  
of any GLB on the device.  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
The device also has 128 I/O cells, each of which is  
directly connected to an I/O pin. Each I/O cell can be  
Copyright©1998LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
November 1998  
2128e_02  
1
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中文翻译

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ISPLSI2128E-100LT176 替代型号

型号 品牌 替代类型 描述 数据表
ISPLSI2128E-135LT176 LATTICE

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