Datasheet > ISPLSI2128VE

ISPLSI2128VE

更新时间： 2024-11-20 23:01:19

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
19页	235K
描述
3.3V In-System Programmable SuperFAST⑩ High Density PLD

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ISPLSI2128VE 数据手册

ispLSI 2128VE

3.3V In-System Programmable

SuperFAST™ High Density PLD

Features

Functional Block Diagram*

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 6000 PLD Gates

Output Routing Pool (ORP)

D7 D6

Output Routing Pool (ORP)

— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs

— 128 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2128V Devices

Logic

Array

GLB

• 3.3V LOW VOLTAGE 2128 ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 250MHz Maximum Operating Frequency

— tpd = 4.0ns Propagation Delay

Global Routing Pool (GRP)

— Electrically Erasable and Reprogrammable

— Non-Volatile

Output Routing Pool (ORP)

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

0139A/2128VE

*128 I/O Version Shown

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

Description

The ispLSI 2128VE is a High Density Programmable

Logic Device available in 128 and 64 I/O-pin versions.

The device contains 128 Registers, eight Dedicated

Input pins, three Dedicated Clock Input pins, two dedi-

cated Global OE input pins and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 2128VE

features in-system programmability through the Bound-

ary Scan Test Access Port (TAP) and is 100% IEEE

1149.1 Boundary Scan Testable. The ispLSI 2128VE

offers non-volatile reprogrammability of the logic, as well

as the interconnect to provide truly reconfigurable sys-

tems.

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

The basic unit of logic on the ispLSI 2128VE device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128VE device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

2128ve_08

12 3 4 5 6 7...19

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与ISPLSI2128VE相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2128VE_04	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE100LB100	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE-100LB100	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE100LB100I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE100LB208	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE-100LB208	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE100LB208I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE-100LBN100	LATTICE	获取价格	EE PLD, 13ns, CMOS, PBGA100, CABGA-100
ISPLSI2128VE100LBN208	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE-100LBN208	LATTICE	获取价格	3.3V In-System Programmable SuperFASTâ¢ High

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