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ISPLSI2128V-60LQ160I PDF预览

ISPLSI2128V-60LQ160I

更新时间: 2024-10-28 22:07:51
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑
页数 文件大小 规格书
15页 151K
描述
3.3V High Density Programmable Logic

ISPLSI2128V-60LQ160I 数据手册

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®
ispLSI 2128V  
3.3V High Density Programmable Logic  
Features  
Functional Block Diagram*  
• HIGH DENSITY PROGRAMMABLE LOGIC  
— 6000 PLD Gates  
— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs  
— 128 Registers  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
Output Routing Pool (ORP)  
D7 D6  
D5  
D4  
Output Routing Pool (ORP)  
D2  
D1  
D0  
D3  
A0  
A1  
C7  
C6  
D
Q
Q
Q
Q
A2  
A3  
C5  
C4  
• 3.3V LOW VOLTAGE 2128 ARCHITECTURE  
D
D
D
— Interfaces with Standard 5V TTL Devices  
— The 128 I/O Pin Version is Fuse Map Compatible  
with 5V ispLSI 2128  
Logic  
Array  
A4  
A5  
C3  
C2  
GLB  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
A6  
A7  
C1  
C0  
fmax = 80 MHz Maximum Operating Frequency  
tpd = 10 ns Propagation Delay  
Global Routing Pool (GRP)  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
B0  
B1  
B2  
B3  
B5  
B6  
B7  
B4  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
0139A/2128V  
*128 I/O Version Shown  
• IN-SYSTEM PROGRAMMABLE  
Description  
— 3.3V In-System Programmability (ISP™) Using  
Boundary Scan Test Access Port (TAP)  
The ispLSI 2128V is a High Density Programmable Logic  
Device available in 128 and 64 I/O-pin versions. The  
device contains 128 Registers, eight Dedicated Input  
pins, three Dedicated Clock Input pins, two dedicated  
Global OE input pins and a Global Routing Pool (GRP).  
The GRP provides complete interconnectivity between  
all of these elements. The ispLSI 2128V features in-  
system programmability through the Boundary Scan  
Test Access Port (TAP). The ispLSI 2128V offers non-  
volatile reprogrammability of the logic, as well as the  
interconnect to provide truly reconfigurable systems.  
— Open-Drain Output Option for Flexible Bus Interface  
Capability, Allowing Easy Implementation of  
Wired-OR or Bus Arbitration Logic  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• THE EASE OF USE AND FAST SYSTEM SPEED OF  
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control  
— Flexible Pin Placement  
The basic unit of logic on the ispLSI 2128V device is the  
Generic Logic Block (GLB). The GLBs are labeled A0, A1  
.. D7 (see Figure 1). There are a total of 32 GLBs in the  
ispLSI 2128V device. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
Copyright©2000LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
September 2000  
2128v_14  
1

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