Datasheet > ISPLSI1016E100LTN44

ISPLSI1016E100LTN44

更新时间： 2024-09-16 05:11:51

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
13页	263K
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In-System Programmable High Density PLD

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Lead-

Package

ispLSI 1016E

Options

vailable!

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 32 I/O Pins, Four Dedicated Inputs

— 96 Registers

— High-Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

Logic

Array

GLB

— Small Logic Block Size for Random Logic

• HIGH-PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 125 MHz Maximum Operating Frequency

— tpd = 7.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

Global Routing Pool (GRP)

CLK

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

0139C1-isp

Description

• IN-SYSTEM PROGRAMMABLE

The ispLSI 1016E is a High Density Programmable Logic

Device containing 96 Registers, 32 Universal I/O pins,

four Dedicated Input pins, three Dedicated Clock Input

pins, one Global OE input pin and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 1016E offers

5Vnon-volatilein-systemprogrammabilityofthelogic,as

well as the interconnect to provide truly reconfigurable

systems. A functional superset of the ispLSI 1016

architecture, the ispLSI 1016E device adds a new global

output enable pin.

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Device for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

The basic unit of logic on the ispLSI 1016E device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1...B7 (see Figure 1). There are a total of 16 GLBs in the

ispLSI 1016E device. Each GLB has 18 inputs, a

programmable AND/OR/Exclusive OR array, and four

outputswhichcanbeconfiguredtobeeithercombinatorial

or registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

— Lead-Free Package Options

to change without notice.

August 2006

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

1016e_09

12 3 4 5 6 7...13

中文翻译

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与ISPLSI1016E100LTN44相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI1016E100LTN44I	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1016E125LJ	LATTICE	获取价格	High-Density Programmable Logic
ISPLSI1016E-125LJ	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1016E125LJI	LATTICE	获取价格	High-Density Programmable Logic
ISPLSI1016E-125LJI	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1016E125LJN	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1016E-125LJN	LATTICE	获取价格	EE PLD, 10ns, 64-Cell, CMOS, PQCC44, LEAD FREE, PLASTIC, LCC-44
ISPLSI1016E125LJNI	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1016E-125LT	LATTICE	获取价格	EE PLD, 10ns, CMOS, PQFP44, 10 X 10 MM, TQFP-44
ISPLSI1016E125LT44	LATTICE	获取价格	High-Density Programmable Logic

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