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ISLA112P25MREP PDF预览

ISLA112P25MREP

更新时间: 2024-11-16 05:39:47
品牌 Logo 应用领域
英特矽尔 - INTERSIL 转换器
页数 文件大小 规格书
29页 851K
描述
Low Power 12-Bit, 250MSPS ADC

ISLA112P25MREP 数据手册

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Low Power 12-Bit, 250MSPS ADC  
ISLA112P25MREP  
Features  
• Programmable Gain, Offset and Skew Control  
• 1.3GHz Analog Input Bandwidth  
• 60fs Clock Jitter  
The ISLA112P25MREP is a low-power 12-bit, 250MSPS  
analog-to-digital converter. Designed with Intersil’s  
proprietary FemtoCharge™ technology on a standard  
CMOS process.  
• Over-Range Indicator  
A serial peripheral interface (SPI) port allows for  
extensive configurability, as well as fine control of various  
parameters such as gain and offset.  
• Selectable Clock Divider: ÷1, ÷2 or ÷4  
• Clock Phase Selection  
• Nap and Sleep Modes  
Digital output data is presented in selectable LVDS or  
CMOS formats. The ISLA112P25MREP is available in a  
72 Ld QFN package with an exposed paddle. Operating  
from a 1.8V supply, performance is specified over the full  
military temperature range (-55°C to +125°C).  
Two’s Complement, Gray Code or Binary Data Format  
• SDR/DDR LVDS-Compatible or LVCMOS Outputs  
• Programmable Built-in Test Patterns  
• Single-Supply 1.8V Operation  
• Pb-Free (RoHS Compliant)  
Applications  
• Power Amplifier Linearization  
• Radar and Satellite Antenna Array Processing  
• Broadband Communications  
VID Features  
• Specifications per DSCC VID V62/10609  
• Full Military Temperature Electrical Performance from  
-55°C to +125°C  
• High-Performance Data Acquisition  
• Communications Test Equipment  
• Controlled Baseline with One Wafer Fabrication Site  
and One Assembly/Test Site  
Key Specifications  
• Full Homogeneous Lot Processing in Wafer Fab  
• No Combination of Wafer Fabrication Lots in Assembly  
• Full Traceability Through Assembly and Test by  
• Date/Trace Code Assignment  
• SNR = 62.7dBFS for f = 105MHz (-1dBFS)  
IN  
• SFDR = 67dBc for f = 105MHz (-1dBFS)  
IN  
Total Power Consumption  
- 310mW @ 250MSPS (SDR Mode)  
- 234mW @ 250MSPS (DDR Mode)  
• Enhanced Process Change Notification  
• Enhanced Obsolescence Management  
• Eliminates Need for Up-Screening a COTS Component  
Block Diagram  
CLKP  
CLKN  
CLKOUTP  
CLOCK  
GENERATION  
CLKOUTN  
D[11:0]P  
D[11:0]N  
VINP  
12-BIT  
250 MSPS  
ADC  
DIGITAL  
ERROR  
CORRECTION  
SHA  
ORP  
ORN  
VINN  
VCM  
LVDS/CMOS  
DRIVERS  
+
OUTFMT  
1.25V  
SPI  
CONTROL  
OUTMODE  
June 25, 2010  
FN7646.0  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  
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