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ISLA112P50IRZ PDF预览

ISLA112P50IRZ

更新时间: 2024-11-16 05:39:47
品牌 Logo 应用领域
英特矽尔 - INTERSIL 转换器
页数 文件大小 规格书
35页 1073K
描述
12-Bit, 500MSPS A/D Converter

ISLA112P50IRZ 数据手册

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12-Bit, 500MSPS A/D Converter  
ISLA112P50  
Features  
• 1.15GHz Analog Input Bandwidth  
• 90fs Clock Jitter  
The ISLA112P50 is a low-power, high-performance,  
500MSPS analog-to-digital converter designed with  
Intersil’s proprietary FemtoCharge® technology on a  
standard CMOS process. The ISLA112P50 is part of a  
pin-compatible portfolio of 8, 10 and 12-bit A/Ds. This  
device an upgrade of the KAD551XP-50 product family  
and is pin similar.  
• Automatic Fine Interleave Correction Calibration  
• Multiple Chip Time Alignment Support via the  
Synchronous Clock Divider Reset  
• Programmable Gain, Offset and Skew control  
• Over-Range Indicator  
The device utilizes two time-interleaved 250MSPS unit  
A/Ds to achieve the ultimate sample rate of 500MSPS. A  
single 500MHz conversion clock is presented to the  
converter, and all interleave clocking is managed  
internally. The proprietary Intersil Interleave Engine  
(I2E) performs automatic fine correction of offset, gain,  
and sample time skew mismatches between the unit  
A/Ds to optimize performance. No external interleaving  
algorithm is required.  
• Clock Phase Selection  
• Nap and Sleep Modes  
Two’s Complement, Gray Code or Binary Data  
Format  
• DDR LVDS-Compatible or LVCMOS Outputs  
• Programmable Test Patterns and Internal  
Temperature Sensor  
A serial peripheral interface (SPI) port allows for  
extensive configurability of the A/D. The SPI also controls  
the interleave correction circuitry, allowing the system to  
issue continuous calibration commands as well as  
configure many dynamic parameters.  
Applications  
• Radar and Electronic/Signal Intelligence  
• Broadband Communications  
• High-Performance Data Acquisition  
Digital output data is presented in selectable LVDS or  
CMOS formats. The ISLA112P50 is available in a  
72-contact QFN package with an exposed paddle.  
Performance is specified over the full industrial  
temperature range (-40°C to +85°C).  
Block Diagram  
Pin-Compatible Family  
SPEED  
MODEL  
ISLA112P50  
RESOLUTION  
(MSPS)  
12  
10  
8
500  
ISLA110P50  
ISLA118P50  
500  
CLKP  
CLKN  
CLKOUTP  
CLKOUTN  
CLOCK  
MANAGEMENT  
500  
Key Specifications  
12-BIT  
250MSPS  
ADC  
• SNR = 65.8dBFS for f = 190MHz (-1dBFS)  
IN  
D[11:0]P  
D[11:0]N  
SHA  
• SFDR = 80dBc for f = 190MHz (-1dBFS)  
IN  
Total Power Consumption = 455mW  
VREF  
ORP  
ORN  
DIGITAL  
ERROR  
VINP  
VINN  
Gain/ Offset/ Skew  
Adjustments  
I2E  
CORRECTION  
OUTFMT  
OUTMODE  
12  
-BIT  
VCM  
SHA  
250MSPS  
ADC  
VREF  
1.25V  
+
SPI  
CONTROL  
June 17, 2010  
FN7604.1  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  

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