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ISLA118P50 PDF预览

ISLA118P50

更新时间: 2024-11-17 14:57:55
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
34页 1745K
描述
8-Bit, 500MSPS A/D Converter

ISLA118P50 数据手册

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DATASHEET  
ISLA118P50  
8-Bit, 500MSPS A/D Converter  
FN7565  
Rev.3.0  
Jul 6, 2021  
The ISLA118P50 is a low-power, high-performance, 500MSPS  
analog-to-digital converter designed with Renesas’ proprietary  
FemtoCharge™ technology on a standard CMOS process. The  
ISLA118P50 is part of a pin-compatible portfolio of 8, 10 and  
12-bit A/Ds. This device an upgrade of the KAD551XP-50  
product family and is pin similar.  
Features  
• 1.15GHz Analog Input Bandwidth  
• 90fs Clock Jitter  
• Automatic Fine Interleave Correction Calibration  
• Multiple Chip Time Alignment Support via the Synchronous  
Clock Divider Reset  
The device utilizes two time-interleaved 250MSPS unit A/Ds to  
achieve the ultimate sample rate of 500MSPS. A single  
500MHz conversion clock is presented to the converter, and all  
interleave clocking is managed internally. The proprietary  
Interleave Engine (I2E) performs automatic fine correction of  
offset, gain, and sample time skew mismatches between the  
unit A/Ds to optimize performance. No external interleaving  
algorithm is required.  
• Programmable Gain, Offset and Skew Control  
• Over-Range Indicator  
• Clock Phase Selection  
• Nap and Sleep Modes  
• Two’s Complement, Gray Code or Binary Data Format  
• DDR LVDS-Compatible or LVCMOS Outputs  
A serial peripheral interface (SPI) port allows for extensive  
configurability of the A/D. The SPI also controls the interleave  
correction circuitry, allowing the system to issue continuous  
calibration commands as well as configure many dynamic  
parameters.  
• Programmable Test Patterns and Internal Temperature  
Sensor  
Applications  
• Radar and Electronic/Signal Intelligence  
• Broadband Communications  
• High-Performance Data Acquisition  
Digital output data is presented in selectable LVDS or CMOS  
formats. The ISLA118P50 is available in a 72-contact QFN  
package with an exposed paddle. Performance is specified  
over the full industrial temperature range (-40°C to +85°C).  
TABLE 1. PIN-COMPATIBLE FAMILY  
SPEED  
MODEL  
ISLA112P50  
RESOLUTION  
(MSPS)  
12  
10  
8
500  
ISLA110P50  
ISLA118P50  
500  
CLKP  
CLKN  
CLKOUTP  
CLKOUTN  
CLOCK  
MANAGEMENT  
500  
Key Specifications  
8 -BIT  
250MSPS  
ADC  
• SNR = 49.9dBFS for f = 190MHz (-1dBFS)  
IN  
D[7:0]P  
D[7:0]N  
SHA  
• SFDR = 68dBc for f = 190MHz (-1dBFS)  
IN  
VREF  
ORP  
ORN  
• Total Power Consumption = 428mW  
DIGITAL  
ERROR  
VINP  
VINN  
Gain/ Offset/ Skew  
Adjustments  
I2E  
CORRECTION  
OUTFMT  
OUTMODE  
8 -BIT  
250MSPS  
ADC  
VCM  
SHA  
VREF  
+
1.25V  
SPI  
CONTROL  
FIGURE 1. BLOCK DIAGRAM  
FN7565 Rev.3.0  
Jul 6, 2021  
Page 1 of 33  
© 2010 Renesas Electronics  

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