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IS93C46A-5PA PDF预览

IS93C46A-5PA

更新时间： 2024-11-21 19:44:03
品牌 Logo 应用领域
美国芯成 - ISSI 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
13页 64K
描述
EEPROM

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中文翻译

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IS93C46A-5PA 技术参数

是否Rohs认证： 不符合生命周期：Active
Reach Compliance Code：compliant风险等级：5.88
JESD-609代码：e0端子面层：Tin/Lead (Sn/Pb)
Base Number Matches：1

IS93C46A-5PA 数据手册

 浏览型号IS93C46A-5PA的Datasheet PDF文件第2页浏览型号IS93C46A-5PA的Datasheet PDF文件第3页浏览型号IS93C46A-5PA的Datasheet PDF文件第4页浏览型号IS93C46A-5PA的Datasheet PDF文件第5页浏览型号IS93C46A-5PA的Datasheet PDF文件第6页浏览型号IS93C46A-5PA的Datasheet PDF文件第7页 
®
IS93C46A IS93C56A IS93C66A ISSI  
1,024/2,048/4,096-BIT SERIAL ELECTRICALLY  
ERASABLE PROM  
PRELIMINARY INFORMATION  
MAY 2002  
FEATURES  
DESCRIPTION  
• Industry-standard Microwire Interface  
— Non-volatile data storage  
The IS93C46A/56A/66A is a low-cost 1kb/2kb/  
4kb non-volatile, ISSI serial EEPROM. It is  
®
— Low voltage operation:  
fabricated using an enhanced CMOS design and  
process. The IS93C46A/56A/66A contain power-  
efficient read/write memory, and organziation of  
either 128/256/512 bytes of 8 bits or 64/128/256  
words of 16 bits. When the ORG pin is  
connected to Vcc or left unconnected, x16 is  
selected; when it is connected to ground, x8 is  
selected. The IS93C46A/56A/66A is fully  
backwards compatible with IS93C46/56/66.  
Vcc = 2.5V to 5.5V  
— Full TTL compatible inputs and outputs  
— Auto increment for efficient data dump  
• User Configured Memory Organization  
— By 16-bit or by 8-bit  
• Hardware and software write protection  
— Defaults to write-disabled state at power-up  
— Software instructions for write-enable/disable  
• Enhanced low voltage CMOS E2PROM  
technology  
• Versatile, easy-to-use Interface  
— Self-timed programming cycle  
— Automatic erase-before-write  
— Programming status indicator  
— Word and chip erasable  
An instruction set controls the operation of the  
devices, including read, write, and mode-enable  
functions. The data out pin (Dout) indicates the  
status of the device during the self-timed non-  
volatile programming cycle. The self-timed write  
cycle includes an automatic erase-before-write  
capability. To protect against inadvertent writes,  
the WRITE instruction is accepted only while the  
chip is in the write-enabled state. Data is written  
once per WRITE instruction to the x8 byte or x16  
word selected. If Chip Select (CS) is brought  
HIGH just after initiation of the write cycle, the  
Dout pin would indicate the Ready/Busy status of  
the write activity.  
— Stop SK anytime for power savings  
• Durable and reliable  
— 40-year data retention after 1M write cycles  
— 1 million write cycles  
— Unlimited read cycles  
— Schmitt-trigger inputs  
FUNCTIONAL BLOCK DIAGRAM  
DUMMY  
BIT  
DOUT  
DATA  
REGISTER  
INSTRUCTION  
REGISTER  
R/W  
AMPS  
DIN  
EEPROM  
ARRAY  
ADDRESS  
REGISTER  
INSTRUCTION  
DECODE,  
CONTROL,  
AND  
ADDRESS  
DECODER  
CS  
128/256/512x16  
64/128/256/x8  
CLOCK  
SK  
GENERATION  
HIGH VOLTAGE  
GENERATOR  
WRITE  
ENABLE  
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
PRELIMINARYINFORMATIONRev. 00A  
1
05/07/02  
1234567...13

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IS93C46B-3GRA ISSI

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 		1,024-BIT SERIAL ELECTRICALLY ERASABLE PROM
IS93C46B-3GRI ISSI

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IS93C46B-3P ISSI

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 		1,024-BIT SERIAL ELECTRICALLY ERASABLE PROM
IS93C46B-3PA ISSI

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 		1,024-BIT SERIAL ELECTRICALLY ERASABLE PROM

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