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IS61SP25616-166TQ PDF预览

IS61SP25616-166TQ

更新时间： 2024-11-08 22:55:31
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
15页 122K
描述
256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM

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IS61SP25616-166TQ 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92最长访问时间：3.5 ns
其他特性：SELF-TIMED WRITE; BURST COUNTER; BYTE WRITE; LINEAR/INTERLEAVED BURST SEQUENCE最大时钟频率 (fCLK)：166 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：4194304 bit内存集成电路类型：CACHE SRAM
内存宽度：16功能数量：1
端子数量：100字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.015 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.21 mA
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

IS61SP25616-166TQ 数据手册

 浏览型号IS61SP25616-166TQ的Datasheet PDF文件第2页浏览型号IS61SP25616-166TQ的Datasheet PDF文件第3页浏览型号IS61SP25616-166TQ的Datasheet PDF文件第4页浏览型号IS61SP25616-166TQ的Datasheet PDF文件第5页浏览型号IS61SP25616-166TQ的Datasheet PDF文件第6页浏览型号IS61SP25616-166TQ的Datasheet PDF文件第7页 
®
IS61SP25616  
IS61SP25618  
256K x 16, 256K x 18 SYNCHRONOUS  
PIPELINED STATIC RAM  
ISSI  
APRIL 2001  
FEATURES  
DESCRIPTION  
The ISSI IS61SP25616 and IS61SP25618 is a high-speed  
synchronous static RAM designed to provide a burstable,  
high-performance memory for high speed networking and  
communication applications. It is organized as 262,144  
words by 16 bits and 18 bits, fabricated with ISSI's  
advanced CMOS technology. The device integrates a 2-bit  
burst counter, high-speed SRAM core, and high-drive  
capability outputs into a single monolithic circuit. All  
synchronous inputs pass through registers controlled by  
a positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control using  
MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
• Common data inputs and data outputs  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be from  
one to four bytes wide as controlled by the write control  
inputs.  
• JEDEC 100-Pin TQFP and  
119-pin PBGA package  
• Single +3.3V, +10%, -5% power supply  
• Power-down snooze mode  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned  
by BWE being LOW. A LOW on GW input would cause all  
bytes to be written.  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-166  
3.5  
6
-150  
3.8  
-133  
4
-5  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
6.7  
7.5  
133  
10  
100  
ns  
Frequency  
166  
150  
MHz  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any  
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
1
04/17/01  
1234567...15

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