Datasheet > 存储 > SRAM> IS61SP25618-166B

IS61SP25618-166B

更新时间： 2024-11-22 22:55:35

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
15页	122K
描述
256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM

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IS61SP25618-166B 数据手册

IS61SP25616

IS61SP25618

256K x 16, 256K x 18 SYNCHRONOUS

PIPELINED STATIC RAM

ISSI

APRIL 2001

FEATURES

DESCRIPTION

The ISSI IS61SP25616 and IS61SP25618 is a high-speed

synchronous static RAM designed to provide a burstable,

high-performance memory for high speed networking and

communication applications. It is organized as 262,144

words by 16 bits and 18 bits, fabricated with ISSI's

advanced CMOS technology. The device integrates a 2-bit

burst counter, high-speed SRAM core, and high-drive

capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be from

one to four bytes wide as controlled by the write control

inputs.

• JEDEC 100-Pin TQFP and

119-pin PBGA package

• Single +3.3V, +10%, -5% power supply

• Power-down snooze mode

Separate byte enables allow individual bytes to be written.

BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned

by BWE being LOW. A LOW on GW input would cause all

bytes to be written.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-166

3.5

-150

3.8

-133

-5

Units

Clock Access Time

Cycle Time

tKC

6.7

7.5

133

100

Frequency

166

150

MHz

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

12 3 4 5 6 7...15

中文翻译

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与IS61SP25618-166B相关器件

型号	品牌	获取价格	描述	数据表
IS61SP25618-166TQ	ISSI	获取价格	256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP25618-5B	ISSI	获取价格	256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP25618-5TQ	ISSI	获取价格	256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP25618-5TQI	ISSI	获取价格	256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP6436-4.5PQ	ETC	获取价格	x36 Fast Synchronous SRAM
IS61SP6436-4.5TQ	ETC	获取价格	x36 Fast Synchronous SRAM
IS61SP6436-4.8PQ	ETC	获取价格	x36 Fast Synchronous SRAM
IS61SP6436-4.8PQI	ETC	获取价格	x36 Fast Synchronous SRAM
IS61SP6436-4.8TQ	ETC	获取价格	x36 Fast Synchronous SRAM
IS61SP6436-4.8TQI	ETC	获取价格	x36 Fast Synchronous SRAM

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