Datasheet > IS61SP6464

IS61SP6464

更新时间： 2024-11-22 22:50:11

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
19页	130K
描述
64K x 64 SYNCHRONOUS PIPELINE STATIC RAM

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IS61SP6464 数据手册

IS61SP6464

ISSI

JANUARY 2004

64K x 64 SYNCHRONOUS

PIPELINE STATIC RAM

FEATURES

DESCRIPTION

TheISSIIS61SP6464isahigh-speed,low-powersynchronous

staticRAMdesignedtoprovideaburstable,high-performance,

secondary cache for the i486™, Pentium™, 680X0™, and

PowerPC™microprocessors. Itisorganizedas65,536words

by64bits,fabricatedwithISSI'sadvancedCMOStechnology.

Thedeviceintegratesa2-bitburstcounter, high-speedSRAM

core, and high-drive capability outputs into a single monolithic

circuit. All synchronous inputs pass through registers con-

trolled by a positive-edge-triggered single clock input.

• Fast access time:

– 117, 100 MHz

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control

using MODE input

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

eight bytes wide as controlled by the write control inputs.

• Five chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 128-Pin TQFP 14mm x 20mm

package

Separatebyteenablesallowindividualbytestobewritten.BW1

controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 controls I/

O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls

I/O33-I/O40,BW6controlsI/O41-I/O48,BW7controlsI/O49-I/

O56, BW8 controls I/O57-I/O64, conditioned by BWE being

LOW. A LOW onGW input would cause all bytes to be written.

• Single +3.3V power supply

• Control pins mode upon power-up:

– MODE in interleave burst mode

– ZZ in normal operation mode

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller) input

pins.Subsequentburstaddressescanbegeneratedinternally

by the IS61SP6464 and controlled by the ADV (burst address

advance) input pin.

These control pins can be connected to GNDQ

or VDDQ to alter their power-up state

Asynchronoussignalsincludeoutputenable(OE),sleepmode

input(ZZ), andburstmodeinput(MODE). AHIGHinputonthe

ZZ pin puts the SRAM in the power-down state. When ZZ is

pulledLOW(ornoconnect),theSRAMnormallyoperatesafter

the wake-up period. A LOW input, i.e., GND^Q, on MODE pin

selects LINEAR Burst. A VDDQ (or no connect) on MODE pin

selects INTERLEAVED Burst.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. C

01/14/04

12 3 4 5 6 7...19

中文翻译

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与IS61SP6464相关器件

型号	品牌	获取价格	描述	数据表
IS61SP6464-100PQ	ISSI	获取价格	64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
IS61SP6464-100PQI	ISSI	获取价格	64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
IS61SP6464-100TQ	ISSI	获取价格	64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
IS61SP6464-100TQI	ISSI	获取价格	64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
IS61SP6464-117PQ	ISSI	获取价格	64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
IS61SP6464-117PQI	ISSI	获取价格	64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
IS61SP6464-117TQ	ISSI	获取价格	64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
IS61SP6464-117TQI	ISSI	获取价格	64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
IS61SP6464-133PQ	ISSI	获取价格	64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
IS61SP6464-133PQI	ISSI	获取价格	64K x 64 SYNCHRONOUS PIPELINE STATIC RAM

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