Datasheet > IS61QDB42M18C-333M3I

IS61QDB42M18C-333M3I

更新时间： 2022-09-29 19:53:06

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
32页	804K
描述
IC SRAM 36M PARALLEL 165LFBGA

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IS61QDB42M18C-333M3I 数据手册

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IS61QDB42M18C

IS61QDB41M36C

Sequence3. Doff# is controlled but goes high before clock being stable.

Because DLL has a risk to be locked with the unstable clock, DLL needs to be reset and locked with the stable input.

a) K-stop to reset. If K or K# stays at VIH or VIL for more than 30nS, DLL will be reset and ready to re-lock. In tKC-

Lock period, DLL will be locked with a new stable value. Device can be ready for normal operation after that.

Power On stage

Unstable Clock Period

K-Stop

Stable Clock period

Read to use

Doff#

>30nS

>tKC-lock for device initialization

VDD

VDDQ

VREF

VIN

Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.

a) Doff# Low to reset. If Doff toggled low to high, DLL will be reset and ready to re-lock. In tKC-Lock period, DLL will

be locked with a new stable value. Device can be ready for normal operation after that.

Power On stage

Unstable Clock Period Doff reset DLL

Stable Clock period

Read to use

Doff#

>tKC-lock for device

initialization

>tDoffLowToReset

VDD

VDDQ

VREF

VIN

Note) Applying DLL reset sequences (sequence 3a, 3b) are also required when operating frequency is changed without power off.

Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A1

04/06/2016

1...5 6 789 10 11...32

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