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IS61QDB44M18-300M3 PDF预览

IS61QDB44M18-300M3

更新时间： 2024-10-13 05:39:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器双倍数据速率时钟
页数 文件大小 规格书
28页 679K
描述
72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

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IS61QDB44M18-300M3 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：15 X 17 MM, 1 MM PITCH, LFBGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.16
Is Samacsys：N最长访问时间：0.45 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：300 MHz
I/O 类型：SEPARATEJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：17 mm
内存密度：75497472 bit内存集成电路类型：DDR SRAM
内存宽度：18功能数量：1
端子数量：165字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.5/1.8,1.8 V
认证状态：Not Qualified座面最大高度：1.4 mm
最小待机电流：1.7 V子类别：SRAMs
最大压摆率：0.8 mA最大供电电压 (Vsup)：1.89 V
最小供电电压 (Vsup)：1.71 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：15 mmBase Number Matches：1

IS61QDB44M18-300M3 数据手册

 浏览型号IS61QDB44M18-300M3的Datasheet PDF文件第2页浏览型号IS61QDB44M18-300M3的Datasheet PDF文件第3页浏览型号IS61QDB44M18-300M3的Datasheet PDF文件第4页浏览型号IS61QDB44M18-300M3的Datasheet PDF文件第5页浏览型号IS61QDB44M18-300M3的Datasheet PDF文件第6页浏览型号IS61QDB44M18-300M3的Datasheet PDF文件第7页 
72 Mb (2M x 36 & 4M x 18)  
.
QUAD (Burst of 4) Synchronous SRAMs  
November 2009  
• Two echo clocks (CQ and CQ) that are delivered  
Features  
simultaneously with data.  
• 2M x 36 or 4M x 18.  
• +1.8V core power supply and 1.5, 1.8V VDDQ  
used with 0.75, 0.9V VREF  
,
• On-chip delay-locked loop (DLL) for wide data  
valid window.  
.
• HSTL input and output levels.  
• Separate read and write ports with concurrent  
read and write operations.  
• Registered addresses, write and read controls,  
byte writes, data in, and data outputs.  
• Synchronous pipeline read with late write opera-  
tion.  
• Full data coherency.  
• Boundary scan using limited set of JTAG 1149.1  
functions.  
• Double data rate (DDR) interface for read and  
write input ports.  
• Byte write capability.  
• Fixed 4-bit burst for read and write operations.  
• Clock stop support.  
• Fine ball grid array (FBGA) package  
- 15mm x 17mm body size  
- 1mm pitch  
• Two input clocks (K and K) for address and con-  
trol registering at rising edges only.  
- 165-ball (11 x 15) array  
• Two input clocks (C and C) for data output con-  
trol.  
• Programmable impedance output drivers via 5x  
user-supplied precision resistor.  
• Industrial temperature available  
Description  
The 72Mb IS61QDB42M36 and  
• Byte writes for burst addresses 2 and 4  
• Data-in for burst addresses 2 and 4  
IS61QDB44M18 are synchronous, high-perfor-  
mance CMOS static random access memory  
(SRAM) devices. These SRAMs have separate I/Os,  
eliminating the need for high-speed bus turnaround.  
The rising edge of K clock initiates the read/write  
operation, and all internal operations are self-timed.  
Refer to the Timing Reference Diagram for Truth  
Table on page 8 for a description of the basic opera-  
tions of these QUAD (Burst of 4) SRAMs.  
Byte writes can change with the corresponding data-  
in to enable or disable writes on a per-byte basis. An  
internal write buffer enables the data-ins to be regis-  
tered one cycle after the write address. The first  
data-in burst is clocked one cycle later than the write  
command signal, and the second burst is timed to  
the following rising edge of the K clock. Two full  
clock cycles are required to complete a write opera-  
tion.  
Read and write addresses are registered on alter-  
nating rising edges of the K clock. Reads and writes  
are performed in double data rate. The following are  
registered internally on the rising edge of the K  
clock:  
During the burst read operation, the data-outs from  
the first and third bursts are updated from output  
registers off the second and fourth rising edges of  
the C clock (starting 1.5 cycles later). The data-outs  
from the second and fourth bursts are updated with  
the third and fifth rising edges of the C clock. The K  
and K clocks are used to time the data-outs when-  
ever the C and C clocks are tied high. Two full clock  
cycles are required to complete a read operation  
• Read/write address  
• Read enable  
• Write enable  
• Byte writes for burst addresses 1 and 3  
• Data-in for burst addresses 1 and 3  
The following are registered on the rising edge of  
the K clock:  
The device is operated with a single +1.8V power  
supply and is compatible with HSTL I/O interfaces.  
Integrated Silicon Solution, Inc.  
1
Rev. B  
11/10/09  
1234567...28

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与IS61QDB44M18-300M3相关器件

型号 品牌 获取价格 描述 数据表
IS61QDB44M18-300M3I ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs
IS61QDB44M18-300M3L ISSI

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 		DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, LEAD FREE, LFBGA-165
IS61QDB44M18A ISSI

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 		2Mx36 and 4Mx18 configuration available
IS61QDB44M18A-300M3L ISSI

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 		QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB451236A ISSI

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 		512Kx36 and 1Mx18 configuration available
IS61QDB451236A-250M3L ISSI

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 		QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDP2B21M18A ISSI

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 		512Kx36 and 1Mx18 configuration available
IS61QDP2B21M18A1 ISSI

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 		512Kx36 and 1Mx18 configuration available
IS61QDP2B21M18A2 ISSI

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 		512Kx36 and 1Mx18 configuration available
IS61QDP2B21M36A ISSI

获取价格

 		1Mx36 and 2Mx18 configuration available

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