IS61QDB42M18C
IS61QDB41M36C
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into the array
on the third write cycle. A read cycle to the last two write addresses produces data from the write buffers. The SRAM
maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written (see
X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table).
Whenever a write is disabled (W# is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust
its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the
SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee
impedance matching is between 175Ω and 350Ω at VDDQ=1.5V. The RQ resistor should be placed less than two inches
away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ should not be
connected to VSS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in
supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances
values. The final impedance value is achieved within 1024 clock cycles.
Clock Consideration
This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock mode to
minimize power and requires only 1024 cycles to restart.
No clocks can be issued until VDD reaches its allowable operating range.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C# are both connected high at power-up
and must never change. Under this condition, K and K# will control the output timings.
Either clock pair must have both polarities switching and must never connect to VREF, as they are not differential
clocks.
Depth Expansion
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending
read and write transactions are always completed prior to deselecting the corresponding port.
Delay Locked Loop (DLL)
Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to
enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match
the clock frequency. Therefore device can have stable output over the temperature and voltage variation.
DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the
AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL
off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or legacy
QUAD mode.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A1
5
04/06/2016
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