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IS61NVP51236-200B2I PDF预览

IS61NVP51236-200B2I

更新时间： 2024-11-25 15:35:31
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
36页 201K
描述
ZBT SRAM, 512KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119

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IS61NVP51236-200B2I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：BGA,针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.5
最长访问时间：3.1 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
内存密度：18874368 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：119
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX36
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

IS61NVP51236-200B2I 数据手册

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IS61NLP25672/IS61NVP25672  
IS61NLP51236/IS61NVP51236  
IS61NLP102418/IS61NVP102418  
®
ISSI  
ADVANCEINFORMATION  
DECEMBER 2002  
256K x 72, 512K x 36 and 1M x 18  
18Mb, PIPELINE 'NO WAIT' STATE  
BUS SRAM  
FEATURES  
DESCRIPTION  
The 18 Meg 'NLP/NVP' product family feature high-speed,  
low-power synchronous static RAMs designed to provide  
a burstable, high-performance, 'no wait' state, device for  
networking and communications applications. They are  
organized as 256K words by 72 bits, 512K words  
by 36 bits and 1M words by 18 bits, fabricated with ISSI's  
advancedCMOStechnology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single R/W (Read/Write) control pin  
• Clock controlled, registered address,  
data and control  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Interleaved or linear burst sequence control using  
MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operations  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKE is HIGH. In this state the internal  
device will hold their previous values.  
• Power Down mode  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
All Read, Write and Deselect cycles are initiated by the  
ADV input. When the ADV is HIGH the internal burst  
counter is incremented. New external addresses can be  
loaded when ADV is LOW.  
• JEDEC 100-pin TQFP, 119-ball PBGA, 165-ball  
PBGA and 209-ball (x72) PBGA packages  
• Power supply:  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock inputs and when WE is LOW.  
Separate byte enables allow individual bytes to be written.  
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
• JTAG Boundary Scan for PBGA packages  
• Industrial temperature available  
A burst mode pin (MODE) defines the order of the burst  
sequence.WhentiedHIGH,theinterleavedburstsequence  
is selected. When tied LOW, the linear burst sequence is  
selected.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-250  
2.6  
4
-200  
3.1  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. 00A  
1
12/11/02  
1234567...36

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与IS61NVP51236-200B2I相关器件

型号 品牌 获取价格 描述 数据表
IS61NVP51236-200B3 ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-200B3I ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-200B3L ISSI

获取价格

 		ZBT SRAM, 512KX36, 3.1ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-1
IS61NVP51236-200TQ ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-200TQI ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-200TQLI ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-250B2I ISSI

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 		ZBT SRAM, 512KX36, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61NVP51236-250B3 ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-250B3I ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-250TQ ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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