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IS61NVP51236B-200TQLI PDF预览

IS61NVP51236B-200TQLI

更新时间： 2024-10-13 22:55:35
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
39页 1970K
描述
IC SRAM 18M PARALLEL 100LQFP

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IS61NVP51236B-200TQLI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LQFP,Reach Compliance Code：compliant
Factory Lead Time：10 weeks风险等级：5.74
最长访问时间：3 nsJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：18874368 bit
内存集成电路类型：STANDARD SRAM内存宽度：36
功能数量：1端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1.6 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

IS61NVP51236B-200TQLI 数据手册

 浏览型号IS61NVP51236B-200TQLI的Datasheet PDF文件第2页浏览型号IS61NVP51236B-200TQLI的Datasheet PDF文件第3页浏览型号IS61NVP51236B-200TQLI的Datasheet PDF文件第4页浏览型号IS61NVP51236B-200TQLI的Datasheet PDF文件第5页浏览型号IS61NVP51236B-200TQLI的Datasheet PDF文件第6页浏览型号IS61NVP51236B-200TQLI的Datasheet PDF文件第7页 
IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B  
IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B  
512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS  
SYNCHRONOUS SRAM  
AUGUST 2019  
FEATURES  
DESCRIPTION  
The 18Meg product family features high-speed, low-  
power synchronous static RAMs designed to provide  
a burstable, high-performance, 'no wait' state,  
device for networking and communications  
applications. They are organized as 512K words by  
36 bits and 1024K words by 18 bits, fabricated with  
ISSI's advanced CMOS technology.  
Incorporating a 'no wait' state feature, wait cycles  
are eliminated when the bus switches from read to  
write, or write to read. This device integrates a 2-bit  
burst counter, high-speed SRAM core, and high-  
drive capability outputs into a single monolithic  
circuit.  
All synchronous inputs pass through registers are  
controlled by a positive-edge-triggered single clock  
input. Operations may be suspended and all  
synchronous inputs ignored when Clock Enable,  
/CKE is HIGH. In this state the internal device will  
hold their previous values.  
•
•
•
•
•
•
100 percent bus utilization  
No wait cycles between Read and Write  
Internal self-timed write cycle  
Individual Byte Write Control  
Single R/W (Read/Write) control pin  
Clock controlled, registered address, data and  
control  
Interleaved or linear burst sequence control  
using MODE input  
Three chip enables for simple depth  
expansion and address pipelining  
Power Down mode  
Common data inputs and data outputs  
/CKE pin to enable clock and suspend  
operation  
JEDEC 100-pin QFP, 165-ball BGA and 119-  
ball BGA packages  
•
•
•
•
•
•
•
Power supply:  
NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
NVVP: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%)  
JTAG Boundary Scan for BGA packages  
Commercial, Industrial and Automotive (x36)  
temperature support  
All Read, Write and Deselect cycles are initiated by  
the ADV input. When the ADV is HIGH the internal  
burst counter is incremented. New external  
addresses can be loaded when ADV is LOW.  
Write cycles are internally self-timed and are  
initiated by the rising edge of the clock inputs and  
when /WE is LOW. Separate byte enables allow  
individual bytes to be written.  
A burst mode pin (MODE) defines the order of the  
burst sequence. When tied HIGH, the interleaved  
burst sequence is selected. When tied LOW, the  
linear burst sequence is selected.  
•
•
•
•
Lead-free available  
For leaded option, please contact ISSI.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
Clock Access Time  
Cycle time  
-250  
2.6  
4
-200  
3.0  
5
Units  
ns  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its  
products at any time without notice. ISSI assumes no liability  
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version  
of this device specification before relying on any  
published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of  
the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products  
are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. D2  
1
08/12/2019  
1234567...39

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与IS61NVP51236B-200TQLI相关器件

型号 品牌 获取价格 描述 数据表
IS61NVP51236B-200TQLI-TR ISSI

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 		IC SRAM 18M PARALLEL 100LQFP
IS61NVP51272-200B1 ISSI

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 		ZBT SRAM, 512KX72, 3.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
IS61NVP51272-200B1I ISSI

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 		ZBT SRAM, 512KX72, 3.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
IS61NVP51272-250B1I ISSI

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 		ZBT SRAM, 512KX72, 2.6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
IS61NVP6436A ISSI

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 		64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP6436A-200TQ ISSI

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 		64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP6436A-200TQI ISSI

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 		64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP6436A-250TQ ISSI

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 		64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP6436A-250TQI ISSI

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 		64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVVF204836B ISSI

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 		100 percent bus utilization

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