Datasheet > 存储 > SRAM> IS61NVP51218A-250TQI

IS61NVP51218A-250TQI

更新时间： 2024-11-21 04:58:39

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
37页	262K
描述
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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IS61NVP51218A-250TQI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TQFP-100	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.82
最长访问时间：	2.6 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	250 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	9437184 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	18
功能数量：	1	端子数量：	100
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	240
电源：	2.5 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.05 A
最小待机电流：	2.38 V	子类别：	SRAMs
最大压摆率：	0.3 mA	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

IS61NVP51218A-250TQI 数据手册

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IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218A

ISSI

256K x 36 and 512K x 18

9Mb, PIPELINE 'NO WAIT' STATE BUS

SRAM

JUNE 2006

FEATURES

DESCRIPTION

The 9 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organizedas256Kwordsby36bitsand512K wordsby18

bits, fabricated with ISSI's advanced CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control using

MODE input

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• JEDEC 100-pin TQFP, 165-ball PBGA and 119-

ball PBGA packages

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

• Power supply:

NVP: V^DD2.5V ( 5ꢀ), VDDQ 2.5V ( 5ꢀ)

NLP: V^DD3.3V ( 5ꢀ), VDDQ 3.3V/2.5V ( 5ꢀ)

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available

FAST ACCESS TIME

Symbol

tKQ

Parameter

-250

2.6

-200

3.1

Units

Clock Access Time

Cycle Time

tKC

Frequency

250

200

MHz

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. B

06/27/06

12 3 4 5 6 7...37

中文翻译

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与IS61NVP51218A-250TQI相关器件

型号	品牌	获取价格	描述	数据表
IS61NVP51218A-250TQI-TR	ISSI	获取价格	暂无描述
IS61NVP51218A-250TQ-TR	ISSI	获取价格	ZBT SRAM, 512KX18, 2.6ns, CMOS, PQFP100,
IS61NVP51236	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-133TQ	ISSI	获取价格	512KX36 ZBT SRAM, 4.2ns, PQFP100, TQFP-100
IS61NVP51236-133TQI	ISSI	获取价格	512KX36 ZBT SRAM, 4.2ns, PQFP100, TQFP-100
IS61NVP51236-166TQ	ISSI	获取价格	512KX36 ZBT SRAM, 3.6ns, PQFP100, TQFP-100
IS61NVP51236-166TQI	ISSI	获取价格	512KX36 ZBT SRAM, 3.6ns, PQFP100, TQFP-100
IS61NVP51236-200B2I	ISSI	获取价格	ZBT SRAM, 512KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61NVP51236-200B3	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-200B3I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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