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IS61NVP51236-133TQ PDF预览

IS61NVP51236-133TQ

更新时间： 2024-10-13 14:51:39
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
17页 108K
描述
512KX36 ZBT SRAM, 4.2ns, PQFP100, TQFP-100

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IS61NVP51236-133TQ 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.8
Is Samacsys：N最长访问时间：4.2 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：18874368 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：100字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

IS61NVP51236-133TQ 数据手册

 浏览型号IS61NVP51236-133TQ的Datasheet PDF文件第2页浏览型号IS61NVP51236-133TQ的Datasheet PDF文件第3页浏览型号IS61NVP51236-133TQ的Datasheet PDF文件第4页浏览型号IS61NVP51236-133TQ的Datasheet PDF文件第5页浏览型号IS61NVP51236-133TQ的Datasheet PDF文件第6页浏览型号IS61NVP51236-133TQ的Datasheet PDF文件第7页 
®
IS61NVP51236 IS61NVP10018  
ISSI  
PRELIMINARY INFORMATION  
SEPTEMBER 2002  
512K x 36 and 1M x 18  
PIPELINE 'NO WAIT' STATE BUS SRAM  
FEATURES  
DESCRIPTION  
The 18 Meg 'NVP' product family feature high-speed,  
low-power synchronous static RAMs designed to provide  
a burstable, high-performance, 'no wait' state, device for  
network and communications customers. They are  
organized as 524, 288 words by 36 bits and 1M words by  
18 bits, fabricated with ISSI's advanced CMOS  
technology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single R/W (Read/Write) control pin  
• Clock controlled, registered address,  
data and control  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Interleaved or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining for TQFP  
All synchronous inputs pass through registers are  
controlled by a positive-edge-triggered single clock input.  
Operations may be suspended and all synchronous  
inputs ignored when Clock Enable, CKE is HIGH. In this  
state the internal device will hold their previous values.  
• Power Down mode  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
• JEDEC 100-pin TQFP, 119 PBGA package  
• VDD +2.5V power supply (± 5%)  
• VDDQ: 2.5V I/O Supply Voltage  
All Read, Write and Deselect cycles are initiated by the  
ADV input. When the ADV is HIGH the internal burst  
counter is incremented. New external addresses can be  
loaded when ADV is LOW.  
• Industrial temperature available  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock inputs and when WE is LOW.  
Separate byte enables allow individual bytes to be  
written.  
A burst mode pin (MODE) defines the order of the burst  
sequence. When tied HIGH, the interleaved burst  
sequence is selected. When tied LOW, the linear burst  
sequence is selected.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-133  
4.2  
-166  
3.6  
6
Units  
ns  
Clock Access Time  
CycleTime  
tKC  
7.5  
ns  
Frequency  
133  
166  
MHz  
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47744  
Rev.00A  
1
09/06/02  
1234567...17

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与IS61NVP51236-133TQ相关器件

型号 品牌 获取价格 描述 数据表
IS61NVP51236-133TQI ISSI

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 		512KX36 ZBT SRAM, 4.2ns, PQFP100, TQFP-100
IS61NVP51236-166TQ ISSI

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 		512KX36 ZBT SRAM, 3.6ns, PQFP100, TQFP-100
IS61NVP51236-166TQI ISSI

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 		512KX36 ZBT SRAM, 3.6ns, PQFP100, TQFP-100
IS61NVP51236-200B2I ISSI

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 		ZBT SRAM, 512KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61NVP51236-200B3 ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-200B3I ISSI

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 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-200B3L ISSI

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 		ZBT SRAM, 512KX36, 3.1ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-1
IS61NVP51236-200TQ ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-200TQI ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51236-200TQLI ISSI

获取价格

 		256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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