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IS61NVP51218A-200TQI-TR PDF预览

IS61NVP51218A-200TQI-TR

更新时间： 2024-11-22 09:32:39
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
37页 533K
描述
ZBT SRAM, 512KX18, 3.1ns, CMOS, PQFP100,

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IS61NVP51218A-200TQI-TR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：compliant风险等级：5.92
最长访问时间：3.1 ns最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：18端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL电源：2.5 V
认证状态：Not Qualified最大待机电流：0.05 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.28 mA标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：QUAD
Base Number Matches：1

IS61NVP51218A-200TQI-TR 数据手册

 浏览型号IS61NVP51218A-200TQI-TR的Datasheet PDF文件第2页浏览型号IS61NVP51218A-200TQI-TR的Datasheet PDF文件第3页浏览型号IS61NVP51218A-200TQI-TR的Datasheet PDF文件第4页浏览型号IS61NVP51218A-200TQI-TR的Datasheet PDF文件第5页浏览型号IS61NVP51218A-200TQI-TR的Datasheet PDF文件第6页浏览型号IS61NVP51218A-200TQI-TR的Datasheet PDF文件第7页 
                                                              
AllꢀRead,WriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ  
                                                             
IS61NLP25636A/IS61NVP25636A  
IS61NLP51218A/IS61NVP51218Aꢀ  
ꢀ
256Kꢀxꢀ36ꢀandꢀ512Kꢀxꢀ18  
9Mb,ꢀPIPELINEꢀ'NOꢀWAIT'ꢀSTATEꢀBUSꢀSRAM  
AUGUSTꢀ2011  
FEATURES  
DESCRIPTION  
Theꢀ9ꢀMegꢀ'NLP/NVP'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ  
low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ  
aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ  
networkingꢀandꢀcommunicationsꢀapplications.ꢀTheyꢀareꢀ  
organizedꢀasꢀ256Kꢀwordsꢀbyꢀ36ꢀbitsꢀandꢀ512Kꢀꢀwordsꢀbyꢀ18ꢀ  
bits,ꢀfabricatedꢀwithꢀISSI'sꢀadvancedꢀCMOSꢀtechnology.  
•ꢀ 100ꢀpercentꢀbusꢀutilization  
•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControl  
•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin  
Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ  
eliminatedꢀwhenꢀtheꢀbusꢀswitchesꢀfromꢀreadꢀtoꢀwrite,ꢀorꢀ  
writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ  
high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ  
intoꢀaꢀsingleꢀmonolithicꢀcircuit.  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ  
dataꢀandꢀcontrol  
ꢀ
•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-  
ingꢀMODEꢀinputꢀ  
Allꢀsynchronousꢀinputsꢀpassꢀthroughꢀregistersꢀareꢀcontrolledꢀ  
byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ  
mayꢀbeꢀsuspendedꢀandꢀallꢀsynchronousꢀinputsꢀignoredꢀ  
whenꢀClockꢀEnable,ꢀCKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ  
deviceꢀwillꢀholdꢀtheirꢀpreviousꢀvalues.  
•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ  
andꢀaddressꢀpipelining  
•ꢀ PowerꢀDownꢀmode  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ CKEꢀpinꢀtoꢀenableꢀclockꢀandꢀsuspendꢀoperation  
input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ  
isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ  
whenꢀADVꢀisꢀLOW.  
•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ165-ballꢀPBGAꢀandꢀ  
119-ballꢀPBGAꢀpackages  
Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ  
byꢀtheꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinputsꢀandꢀwhenꢀWEꢀisꢀ  
LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ  
written.  
•ꢀ Powerꢀsupply:ꢀ  
NVP:ꢀVdd 2.5Vꢀ( ꢀ5%),ꢀVddqꢀ2.5Vꢀ( ꢀ5%)  
NLP:ꢀVddꢀ3.3Vꢀ( ꢀ5%),ꢀVddqꢀ3.3V/2.5Vꢀ( ꢀ5%)  
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackages  
•ꢀ Industrialꢀtemperatureꢀavailable  
•ꢀ Lead-freeꢀavailable  
ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdefinesꢀtheꢀorderꢀofꢀtheꢀburstꢀ  
sequence.WhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ  
isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ  
selected.  
FASTꢀACCESSꢀTIME  
ꢀ
ꢀ
ꢀ
ꢀ
Symbolꢀ  
Parameterꢀ  
-250ꢀ  
2.6ꢀ  
4ꢀ  
-200ꢀ  
3.1ꢀ  
5ꢀ  
Units  
ns  
tkqꢀ  
tkcꢀ  
ꢀ
ClockꢀAccessꢀTimeꢀ  
CycleꢀTimeꢀ  
ns  
Frequencyꢀ  
250ꢀ  
200ꢀ  
MHz  
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀnotice.ꢀꢀꢀISSIꢀassumesꢀnoꢀ  
liabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlatestꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀ  
anyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ  
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀ  
failureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀunlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀ  
assuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:  
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;  
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand  
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ  
1
Rev.ꢀ Hꢀ  
08/09/2011  
1234567...37

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与IS61NVP51218A-200TQI-TR相关器件

型号 品牌 获取价格 描述 数据表
IS61NVP51218A-200TQ-TR ISSI

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 		ZBT SRAM, 512KX18, 3.1ns, CMOS, PQFP100,
IS61NVP51218A-250B2 ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250B2I ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250B2-TR ISSI

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 		暂无描述
IS61NVP51218A-250B3 ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250B3I ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250B3-TR ISSI

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 		ZBT SRAM, 512KX18, 2.6ns, CMOS, PBGA165
IS61NVP51218A-250TQ ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250TQI ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250TQI-TR ISSI

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 		暂无描述

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