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IS61NVP51218A-200TQ-TR PDF预览

IS61NVP51218A-200TQ-TR

更新时间： 2024-11-21 12:59:23
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
37页 262K
描述
ZBT SRAM, 512KX18, 3.1ns, CMOS, PQFP100,

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IS61NVP51218A-200TQ-TR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：compliant风险等级：5.92
最长访问时间：3.1 ns最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：18端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL电源：2.5 V
认证状态：Not Qualified最大待机电流：0.045 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.27 mA标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：QUAD
Base Number Matches：1

IS61NVP51218A-200TQ-TR 数据手册

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®
IS61NLP25636A/IS61NVP25636A  
IS61NLP51218A/IS61NVP51218A  
ISSI  
256K x 36 and 512K x 18  
9Mb, PIPELINE 'NO WAIT' STATE BUS  
SRAM  
JUNE 2006  
FEATURES  
DESCRIPTION  
The 9 Meg 'NLP/NVP' product family feature high-speed,  
low-power synchronous static RAMs designed to provide  
a burstable, high-performance, 'no wait' state, device for  
networking and communications applications. They are  
organizedas256Kwordsby36bitsand512K wordsby18  
bits, fabricated with ISSI's advanced CMOS technology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single R/W (Read/Write) control pin  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Clock controlled, registered address,  
data and control  
• Interleaved or linear burst sequence control using  
MODE input  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operations  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKE is HIGH. In this state the internal  
device will hold their previous values.  
• Three chip enables for simple depth expansion  
and address pipelining  
• Power Down mode  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
All Read, Write and Deselect cycles are initiated by the  
ADV input. When the ADV is HIGH the internal burst  
counter is incremented. New external addresses can be  
loaded when ADV is LOW.  
• JEDEC 100-pin TQFP, 165-ball PBGA and 119-  
ball PBGA packages  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock inputs and when WE is LOW.  
Separate byte enables allow individual bytes to be written.  
• Power supply:  
NVP: VDD 2.5V ( 5ꢀ), VDDQ 2.5V ( 5ꢀ)  
NLP: VDD 3.3V ( 5ꢀ), VDDQ 3.3V/2.5V ( 5ꢀ)  
A burst mode pin (MODE) defines the order of the burst  
sequence.WhentiedHIGH,theinterleavedburstsequence  
is selected. When tied LOW, the linear burst sequence is  
selected.  
• JTAG Boundary Scan for PBGA packages  
• Industrial temperature available  
• Lead-free available  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-250  
2.6  
4
-200  
3.1  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
Rev. B  
06/27/06  
1234567...37

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与IS61NVP51218A-200TQ-TR相关器件

型号 品牌 获取价格 描述 数据表
IS61NVP51218A-250B2 ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250B2I ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250B2-TR ISSI

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 		暂无描述
IS61NVP51218A-250B3 ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250B3I ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250B3-TR ISSI

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 		ZBT SRAM, 512KX18, 2.6ns, CMOS, PBGA165
IS61NVP51218A-250TQ ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250TQI ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250TQI-TR ISSI

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 		暂无描述
IS61NVP51218A-250TQ-TR ISSI

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 		ZBT SRAM, 512KX18, 2.6ns, CMOS, PQFP100,

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