Datasheet > IS61NLF409618B

IS61NLF409618B

更新时间： 2024-09-17 01:01:31

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
38页	1511K
描述
100 percent bus utilization

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS61NLF409618B 数据手册

IS61NLF204836B/IS61NVF/NVVF204836B

IS61NLF409618B/IS61NVF/NVVF409618B

2M x 36 and 4M x 18

72Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM

ADVANCED INFORMATION

FEBRUARY 2013

FEATURES

DESCRIPTION

The72Megproductfamilyfeatureshigh-speed,low-power

synchronousstaticRAMsdesignedtoprovideaburstable,

high-performance, 'no wait' state, device for networking

and communications applications. They are organized as

2,096,952 words by 36 bits and 4,193,904 words by 18

bits, fabricated with ISSI's advanced CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single Read/Write control pin

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control us-

ing MODE input

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

AllRead,WriteandDeselectcyclesareinitiatedbytheADV

input. When the ADV is HIGH the internal burst counter

is incremented. New external addresses can be loaded

when ADV is LOW.

• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-

ball PBGA packages

Write cycles are internally self-timed and are initiated

by the rising edge of the clock inputs and when WE is

LOW. Separate byte enables allow individual bytes to be

written.

• Power supply:

NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)

NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)

NVVF: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)

A burst mode pin (MODE) deﬁnes the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available

FAST ACCESS TIME

Symbol

Parameter

6.5

7.5

133

7.5

8.5

117

Units

tkq

Clock Access Time

Cycle Time

tkc

Frequency

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00C

02/20/2013

12 3 4 5 6 7...38

中文翻译

下载PDF

与IS61NLF409618B相关器件

型号	品牌	获取价格	描述	数据表
IS61NLF51218	ISSI	获取价格	SRAM
IS61NLF51218-9TQ	ISSI	获取价格	ZBT SRAM, 512KX18, 9ns, CMOS, PQFP100, TQFP-100
IS61NLF51218A	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51218A-6.5B2	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51218A-6.5B2I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51218A-6.5B3	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51218A-6.5B3I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51218A-6.5TQ	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51218A-6.5TQI	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51218A-6.5TQL	ISSI	获取价格	ZBT SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100

与IS61NLF409618B相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

9
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

8
SL74HC10N：高性能三输入与非门解析
2024-09-03

90
AIC1781A 电池充电控制器深度解析
2024-09-03

80

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61NLF409618B

IS61NLF409618B 数据手册

与IS61NLF409618B相关器件

与IS61NLF409618B相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61NLF409618B

IS61NLF409618B 数据手册

与IS61NLF409618B相关器件

与IS61NLF409618B相关文章

您还可以找

您在本页遇到什么问题？