Datasheet > IS61NLF51218B-7.5TQLI

IS61NLF51218B-7.5TQLI

更新时间： 2024-11-27 19:48:27

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器内存集成电路
页数	文件大小	规格书
36页	880K
描述
ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, LQFP-100

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IS61NLF51218B-7.5TQLI 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	LQFP,	Reach Compliance Code：	compliant
HTS代码：	8542.32.00.41	Factory Lead Time：	10 weeks
风险等级：	5.73	最长访问时间：	7.5 ns
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	9437184 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	18	功能数量：	1
端子数量：	100	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

IS61NLF51218B-7.5TQLI 数据手册

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IS61NLF25636B/IS61NVF/NVVF25636B

IS61NLF51218B/IS61NVF/NVVF51218B

MAY 2016

256K x 36 and 512K x 18

9Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM

FEATURES

DESCRIPTION

The 9 Meg product family features high-speed, low-power

synchronousstaticRAMsdesignedtoprovideaburstable,

high-performance,'nowait'state,devicefornetworkingand

communicationsapplications.Theyareorganizedas256K

words by 36 bits and 512K words by 18 bits, fabricated

with ISSI's advanced CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single Read/Write control pin

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control us-

ing MODE input

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

AllRead,WriteandDeselectcyclesareinitiatedbytheADV

input. When the ADV is HIGH the internal burst counter

is incremented. New external addresses can be loaded

when ADV is LOW.

• JEDEC 100-pin QFP, 119-ball BGA, and 165-

ball BGA packages

Write cycles are internally self-timed and are initiated

by the rising edge of the clock inputs and when WE is

LOW. Separate byte enables allow individual bytes to be

written.

• Power supply:

NLF: V^dd3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)

NVF: V^dd2.5V (± 5%), Vddq 2.5V (± 5%)

NVVF: V^dd1.8V (± 5%), Vddq 1.8V (± 5%)

A burst mode pin (MODE) deﬁnes the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

• JTAG Boundary Scan for BGA packages

• Industrial temperature available

• Lead-free available

FAST ACCESS TIME

Symbol

Parameter

6.5

7.5

133

7.5

8.5

117

Units

tkq

Clock Access Time

Cycle Time

tkc

Frequency

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. A1

05/23/2016

12 3 4 5 6 7...36

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与IS61NLF51218B-7.5TQLI相关器件

型号	品牌	获取价格	描述	数据表
IS61NLF51236	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51236-6.5B3	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51236-6.5B3I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51236-6.5TQ	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51236-6.5TQI	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51236-7.5B3	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51236-7.5B3I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51236-7.5B3I-TR	ISSI	获取价格	IC SRAM 18M PARALLEL 165TFBGA
IS61NLF51236-7.5TQ	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51236-7.5TQI	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

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