Datasheet > IS61LPS51236A

IS61LPS51236A

更新时间： 2024-11-18 04:58:35

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
34页	220K
描述
256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

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IS61LPS51236A 数据手册

IS61VPS25672A IS61LPS25672A

IS61VPS51236A IS61LPS51236A

IS61VPS102418A IS61LPS102418A

ISSI

256K x 72, 512K x 36, 1024K x 18

18Mb SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT STATIC RAM

FEBRUARY 2005

DESCRIPTION

FEATURES

The ISSIIS61LPS/VPS51236A,IS61LPS/VPS102418A,

andIS61LPS/VPS25672Aarehigh-speed,low-powersyn-

chronous staticRAMs designedtoprovideburstable, high-

performance memory for communication and networking

applications. The IS61LPS/VPS51236A is organized as

524,288 words by 36 bits, the IS61LPS/VPS102418A is

organizedas1,048,576wordsby18bits,andtheIS61LPS/

VPS25672A is organized as 262,144 words by 72 bits.

Fabricated with ISSI's advanced CMOS technology, the

deviceintegratesa2-bitburstcounter,high-speedSRAM

core,andhigh-drivecapabilityoutputsintoasinglemono-

lithic circuit. All synchronous inputs pass through regis-

ters controlled by a positive-edge-triggered single clock

input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

Write cycles are internally self-timed and are initiated by

therisingedgeoftheclockinput. Writecyclescanbeone

tofourbyteswideascontrolledbythewritecontrolinputs.

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

Separatebyteenablesallowindividualbytestobewritten.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx). In addition, Global

Write (GW) is available for writing all bytes at one time,

regardless of the byte write controls.

LPS: V^DD3.3V + 5%, VDDQ 3.3V/2.5V + 5%

VPS: V^DD2.5V + 5%, VDDQ 2.5V + 5%

• JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball

PBGA, and 209-ball (x72) packages

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

inputpins.Subsequentburstaddressescanbegenerated

internally and controlled by the ADV (burst address

advance) input pin.

• Lead-free available

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

250

2.6

200

3.1

Units

Clock Access Time

Cycle Time

tKC

Frequency

250

200

MHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. D

02/11/05

12 3 4 5 6 7...34

中文翻译

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与IS61LPS51236A相关器件

型号	品牌	获取价格	描述	数据表
IS61LPS51236A-200B2	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS51236A-200B2I	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS51236A-200B2LI	ISSI	获取价格	256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51236A-200B3	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS51236A-200B3I	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS51236A-200B3LI	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS51236A-200TQ	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS51236A-200TQI	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS51236A-200TQLI	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS51236A-250B2	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC

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