Datasheet > IS61LPS25618EC-200B3

IS61LPS25618EC-200B3

更新时间： 2024-11-14 00:23:27

品牌	Logo	应用领域
美国芯成 - ISSI		时钟静态存储器内存集成电路
页数	文件大小	规格书
36页	2323K
描述
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM

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IS61LPS25618EC-200B3 技术参数

是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	TBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.79	最长访问时间：	3.1 ns
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	长度：	15 mm
内存密度：	4718592 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	18	功能数量：	1
端子数量：	165	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	并行/串行：	PARALLEL
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大待机电流：	0.08 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.21 mA	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	13 mm

IS61LPS25618EC-200B3 数据手册

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IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC

IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC

128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT SRAM

OCTOBER 2015

FEATURES

DESCRIPTION

The 4Mb product family features high-speed, low-power

synchronous static RAMs designed to provide burstable,

high-performance memory for communication and

networking applications. The IS61(64)LPS/VPS12836EC are

organized as 131,072 words by 36bits. The

IS61(64)LPS/VPS12832EC are organized as 131,072 words by

32bits. The IS61(64)LPS/VPS25618EC are organized as

262,144 words by 18 bits. Fabricated with ISSI's advanced

CMOS technology, the device integrates a 2-bit burst

counter, high-speed SRAM core, and high-drive capability

outputs into a single monolithic circuit. All synchronous

inputs pass through registers controlled by a positive-

edge-triggered single clock input.



Internal self-timed write cycle

Individual Byte Write Control and Global Write

Clock controlled, registered address, data and

control



Burst sequence control using MODE input

Three chip enable option for simple depth

expansion and address pipelining

Common data inputs and data outputs

Auto Power-down during deselect

Single cycle deselect



Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Snooze MODE for reduced-power standby

JEDEC 100-pin QFP, 165-ball BGA and 119-

ball BGA packages

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (/BWE) input combined with one or more

individual byte write signals (/BWx). In addition, Global

Write (/GW) is available for writing all bytes at one time,

regardless of the byte write controls.



Power supply:

LPS: V_DD3.3V (± 5%), V_DDQ3.3V/2.5V (± 5%)

VPS: V_DD2.5V (± 5%), V_DDQ2.5V (± 5%)

JTAG Boundary Scan for BGA packages

Industrial and Automotive temperature support

Lead-free available

Bursts can be initiated with either /ADSP (Address Status

Processor) or /ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the /ADV (burst address

advance) input pin.



Error Detection and Error Correction

The mode pin is used to select the burst sequence order.

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

Clock Access Time

Cycle time

-250

2.6

-200

3.1

Units

tKC

fMAX

Frequency

250

200

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D1

10/5/2015

12 3 4 5 6 7...36

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与IS61LPS25618EC-200B3相关器件

型号	品牌	获取价格	描述	数据表
IS61LPS25618EC-200B3I	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200B3L	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200B3LI	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200TQ	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200TQI	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200TQL	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200TQLI	ISSI	获取价格	Cache SRAM, 256KX18, 3.1ns, CMOS, PQFP100, TQFP-100
IS61LPS25618EC-250B2	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-250B2I	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-250B2L	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM

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