5秒后页面跳转
捷配首页

Datasheet > IS49NLS93200-25BL
IS49NLS93200-25BL PDF预览

IS49NLS93200-25BL

更新时间： 2024-02-05 12:18:57
品牌 Logo 应用领域
美国芯成 - ISSI 时钟动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
33页 1365K
描述
IC DRAM 288M PARALLEL 144FCBGA

阅读下载

中文翻译

获取价格

IS49NLS93200-25BL 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：TBGA, BGA144,12X18,40/32
针数：144Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.28
Factory Lead Time：13 weeks 6 days风险等级：5.7
访问模式：MULTI BANK PAGE BURST最长访问时间：2.5 ns
其他特性：AUTO REFRESH最大时钟频率 (fCLK)：400 MHz
I/O 类型：SEPARATE交错的突发长度：2,4,8
JESD-30 代码：R-PBGA-B144长度：18.5 mm
内存密度：301989888 bit内存集成电路类型：DDR DRAM
内存宽度：9功能数量：1
端口数量：1端子数量：144
字数：33554432 words字数代码：32000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32MX9
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装等效代码：BGA144,12X18,40/32
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
电源：1.5/1.8,1.8,2.5 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.048 A
子类别：DRAMs最大压摆率：0.97 mA
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM宽度：11 mm
Base Number Matches：1

IS49NLS93200-25BL 数据手册

 浏览型号IS49NLS93200-25BL的Datasheet PDF文件第2页浏览型号IS49NLS93200-25BL的Datasheet PDF文件第3页浏览型号IS49NLS93200-25BL的Datasheet PDF文件第4页浏览型号IS49NLS93200-25BL的Datasheet PDF文件第5页浏览型号IS49NLS93200-25BL的Datasheet PDF文件第6页浏览型号IS49NLS93200-25BL的Datasheet PDF文件第7页 
IS49NLS93200,IS49NLS18160  
288Mb (x9, x18) Separate I/O RLDRAM2 Memory  
JANUARY 2020  
FEATURES  
400MHz DDR operation (800Mb/s/pin data rate)  
14.4 Gb/s peak bandwidth (x18 Separate I/O at 400  
MHz clock frequency)  
Reduced cycle time (15ns at 400MHz)  
32ms refresh (8K refresh for each bank; 64K refresh  
command must be issued in total each 32ms)  
8 internal banks  
Non-multiplexed addresses (address multiplexing  
option available)  
SRAM-type interface  
Programmable READ latency (RL), row cycle time,  
and burst sequence length  
Balanced READ and WRITE latencies in order to  
optimize data bus utilization  
Data mask signals (DM) to mask signal of WRITE  
data; DM is sampled on both edges of DK.  
Differential input clocks (CK, CK#)  
Differential input data clocks (DKx, DKx#)  
On-die DLL generates CK edge-aligned data and  
output data clock signals  
Data valid signal (QVLD)  
HSTL I/O (1.5V or 1.8V nominal)  
25-60Ω matched impedance outputs  
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O  
On-die termination (ODT) RTT  
IEEE 1149.1 compliant JTAG boundary scan  
Operating temperature:  
Commercial  
(TC = 0° to +95°C; TA = 0°C to +70°C),  
Industrial  
(TC = -40°C to +95°C; TA = -40°C to +85°C)  
OPTIONS  
Package:  
144-ball WBGA (lead-free)  
Configuration:  
32Mx9  
16Mx18  
Clock Cycle Timing:  
Speed Grade  
-25E  
15  
-25  
20  
-33  
20  
Unit  
ns  
tRC  
tCK  
2.5  
2.5  
3.3  
ns  
Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the  
latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
RLDRAMis a registered trademark of Micron Technology, Inc.  
Integrated Silicon Solution, Inc. – www.issi.com –  
Rev. B, 01/22/2020  
1
1234567...33

中文翻译

下载PDF

与IS49NLS93200-25BL相关器件

型号 品牌 获取价格 描述 数据表
IS49NLS93200-25BLI ISSI

获取价格

 		IC DRAM 288M PARALLEL 144FCBGA
IS49NLS93200-25WBLI ISSI

获取价格

 		DDR DRAM, 32MX9, CMOS, PBGA144, WFBGA-144
IS49NLS93200-33B ISSI

获取价格

 		IC DRAM 288M PARALLEL 144FCBGA
IS49NLS93200-33BI ISSI

获取价格

 		IC DRAM 288M PARALLEL 144FCBGA
IS49NLS93200-33BL ISSI

获取价格

 		IC DRAM 288M PARALLEL 144FCBGA
IS49NLS93200-33BLI ISSI

获取价格

 		IC DRAM 288M PARALLEL 144FCBGA
IS49NLS93200-33WBLI ISSI

获取价格

 		DDR DRAM, 32MX9, CMOS, PBGA144, WFBGA-144
IS49NLS96400 ISSI

获取价格

 		576Mb (x9, x18) Separate I/O RLDRAM 2 Memo
IS49NLS96400-18BL ISSI

获取价格

 		DDR DRAM, 64MX9, 1.875ns, CMOS, PBGA144, 11 X 18.50 MM, LEAD FREE, FBGA-144
IS49NLS96400A ISSI

获取价格

 		8 internal banks

与IS49NLS93200-25BL相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证