Datasheet > 存储 > DRAM> IS43R16800A-6TL

IS43R16800A-6TL

更新时间： 2024-11-25 04:23:03

品牌	Logo	应用领域
美国芯成 - ISSI		存储内存集成电路光电二极管动态存储器双倍数据速率时钟
页数	文件大小	规格书
47页	518K
描述
8Meg x 16 128-MBIT DDR SDRAM

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技术参数
数据手册

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IS43R16800A-6TL 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TSOP2
包装说明：	TSOP2, TSSOP66,.46	针数：	66
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.02	风险等级：	5.57
Is Samacsys：	N	访问模式：	FOUR BANK PAGE BURST
最长访问时间：	0.7 ns	其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	166 MHz	I/O 类型：	COMMON
交错的突发长度：	2,4,8	JESD-30 代码：	R-PDSO-G66
JESD-609代码：	e3	长度：	22.22 mm
内存密度：	134217728 bit	内存集成电路类型：	DDR DRAM
内存宽度：	16	湿度敏感等级：	3
功能数量：	1	端口数量：	1
端子数量：	66	字数：	8388608 words
字数代码：	8000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	8MX16	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP2
封装等效代码：	TSSOP66,.46	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	2.5 V	认证状态：	Not Qualified
刷新周期：	4096	座面最大高度：	1.2 mm
自我刷新：	YES	连续突发长度：	2,4,8
最大待机电流：	0.003 A	子类别：	DRAMs
最大压摆率：	0.35 mA	最大供电电压 (Vsup)：	2.7 V
最小供电电压 (Vsup)：	2.3 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	10.16 mm	Base Number Matches：	1

IS43R16800A-6TL 数据手册

IS43R16800A-6

ISSI

PRELIMINARY INFORMATION

APRIL 2006

8Meg x 16

128-MBIT DDR SDRAM

FEATURES

DEVICE OVERVIEW

• Clock Frequency: 166, 133 MHz

• Power supply (VDD and VDDQ): 2.5V

• SSTL 2 interface

ISSI’s 128-Mbit DDR SDRAM achieves high-speed data

transfer using pipeline architecture and two data word

accesses per clock cycle. The 134,217,728-bit memory

array is internally organized as four banks of 32M-bit to

allowconcurrentoperations. ThepipelineallowsRead

and Write burst accesses to be virtually continuous, with

the option to concatenate or truncate the bursts. The

programmable features of burst length, burst sequence

and CAS latency enable further advantages. The device

is available in 16-bit data word size. Input data is regis-

tered on the I/O pins on both edges of Data Strobe

signal(s), while output data is referenced to both edges of

Data Strobe and both edges of CK. Commands are

registered on the positive edges of CK. Auto Refresh,

Active Power Down, and Pre-charge Power Down modes

are enabled by using clock enable (CKE) and other

inputs in an industry-standard sequence. All input and

output voltage levels are compatible with SSTL 2.

• Four internal banks to hide row Pre-charge

and Active operations

• Commands and addresses register on positive

clock edges (CK)

• Bi-directional Data Strobe signal for data cap-

ture

• Differential clock inputs (CK and CK) for

two data accesses per clock cycle

• Data Mask feature for Writes supported

• DLL aligns data I/O and Data Strobe transitions

with clock inputs

• Half-strength and Matched drive strength

options

IS43R16800A-6

1M x16x8 Banks

VDD: 2.5V

• Programmable burst length for Read and Write

operations

• Programmable CAS Latency (2, 2.5 clocks)

VDDQ: 2.5V

• Programmable burst sequence: sequential or

66-pinTSOP-II

interleaved

• Burst concatenation and truncation supported

for maximum data throughput

KEY TIMING PARAMETERS

• Auto Pre-charge option for each Read or Write

burst

Parameter

-6

Unit

DDR333

• 4096 refresh cycles every 64ms

• Auto Refresh and Self Refresh Modes

Clock Cycle Time

CAS Latency = 3

CAS Latency = 2.5

CAS Latency = 2

—

7.5

• Pre-charge Power Down and Active Power

Down Modes

Clock Frequency

CAS Latency = 3

CAS Latency = 2.5

CAS Latency = 2

• Lead-free Availability

—

166

133

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00A

04/04/06

12 3 4 5 6 7...47

中文翻译

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与IS43R16800A-6TL相关器件

型号	品牌	获取价格	描述	数据表
IS43R16800CC	ISSI	获取价格	Commands entered on each positive CLK edge
IS43R16800CC-5TL	ISSI	获取价格	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, LEAD FREE, TSOP2-66
IS43R16800CC-5TLI	ISSI	获取价格	Commands entered on each positive CLK edge
IS43R16800CC-5TL-TR	ISSI	获取价格	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, LEAD FREE, TSOP2-66
IS43R16800CC-6TL	ISSI	获取价格	Commands entered on each positive CLK edge
IS43R16800CC-6TLI	ISSI	获取价格	Commands entered on each positive CLK edge
IS43R16800CC-6TL-TR	ISSI	获取价格	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, LEAD FREE, TSOP2-66
IS43R16800E	ISSI	获取价格	Auto Refresh and Self Refresh Modes
IS43R32160D-5BL	ISSI	获取价格	DDR DRAM, 16MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MO-205, LFBG
IS43R32160D-5BLI	ISSI	获取价格	DDR DRAM, 16MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MO-205, LFBG

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