Datasheet > IS43R16800CC-6TL

IS43R16800CC-6TL

更新时间： 2024-11-26 01:07:07

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
37页	748K
描述
Commands entered on each positive CLK edge

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IS43R16800CC-6TL 数据手册

IS43R16800CC

8Mx16

128Mb DDR Synchronous DRAM

JUNE 2009

FEATURES:

•ꢀ Vd d =Vd d q = 2.5V+0.2V (-5, -6, -75)

•ꢀ Double data rate architecture; two data transfers

per clock cycle.

•ꢀ Bidirectional , data strobe (DQS) is transmitted/

received with data

•ꢀ Differential clock input (CLK and /CLK)

DESCRIPTION:

IS43R16800CC is a 4-bank x 2,097,152-word x 16bit

double data rate synchronous DRAM , with SSTL_2

interface. All control and address signals are referenced

to the rising edge of CLK. Input data is registered on

both edges of data strobe, and output data and data

strobe are referenced on both edges of CLK. The device

achieves very high speed clock rate up to 200 MHz.

•ꢀ DLL aligns DQ and DQS transitions with CLK

transitions edges of DQS

•ꢀ Commands entered on each positive CLK edge;

•ꢀ Data and data mask referenced to both edges of

KEY TIMING PARAMETERS

Parameter

-5

-6

-75 Unit

DQS

Clk Cycle Time

•ꢀ 4 bank operation controlled by BA0 , BA1

CAS Latency = 3

CAS Latency = 2.5

CAS Latency = 2

7.5

(Bank Address)

•ꢀ /CAS latency -2.0 / 2.5 / 3.0 (programmable) ;

Burst length -2 / 4 / 8 (programmable)

Burst type -Sequential / Interleave (program-

mable)

Clk Frequency

CAS Latency = 3

CAS Latency = 2.5

CAS Latency = 2

200

133

167

133

133 MHz

•ꢀ Auto precharge/ All bank precharge controlled

by A10

Access Time from Clock

CAS Latency = 3

•ꢀ 4096 refresh cycles / 64ms (4 banks concurrent

+0.70 +0.70 +0.75 ns

refresh)

CAS Latency = 2.5 +0.70 +0.70 +0.75 ns

CAS Latency = 2 +0.75 +0.75 +0.75 ns

•ꢀ Auto refresh and Self refresh

•ꢀ Row address A0-11 / Column address A0-8

•ꢀ SSTL_2 Interface

•ꢀ Package:

66-pin TSOP II

•ꢀ Temperature Range:

Commercial (0^oC to +70^oC)

Industrial (-40^oC to +85^oC)

ADDRESS TABLE

Parameter

8M x 16

Conﬁguration

Bank Address Pins

2M x 16 x 4 banks

BA0, BA1

Autoprecharge Pins

Row Addresses

Column Addresses

Refresh Count

A10/AP

A0 – A11

A0 – A8

4096 / 64ms

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the

latest version of this device speciﬁcation before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc.

Rev. A

06/01/09

12 3 4 5 6 7...37

中文翻译

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与IS43R16800CC-6TL相关器件

型号	品牌	获取价格	描述	数据表
IS43R16800CC-6TLI	ISSI	获取价格	Commands entered on each positive CLK edge
IS43R16800CC-6TL-TR	ISSI	获取价格	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, LEAD FREE, TSOP2-66
IS43R16800E	ISSI	获取价格	Auto Refresh and Self Refresh Modes
IS43R32160D-5BL	ISSI	获取价格	DDR DRAM, 16MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MO-205, LFBG
IS43R32160D-5BLI	ISSI	获取价格	DDR DRAM, 16MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MO-205, LFBG
IS43R32160D-5BL-TR	ISSI	获取价格	IC DRAM 512M PARALLEL 144LFBGA
IS43R32160D-6BL	ISSI	获取价格	DDR DRAM, 16MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MO-205, LFBG
IS43R32160D-6BLI	ISSI	获取价格	DDR DRAM, 16MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MO-205, LFBG
IS43R32160D-6BLI-TR	ISSI	获取价格	Cache DRAM Module, 16MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MO-
IS43R32160D-6BL-TR	ISSI	获取价格	Cache DRAM Module, 16MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MO-

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