IS43R83200D
IS43/46R16160D, IS43/46R32800D
8Mx32,ꢀ16Mx16,ꢀ32Mx8ꢀ
256MbꢀDDRꢀSDRAM
JUNEꢀ2012
ꢀ
FEATURES
DEVICEꢀOVERVIEW
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.5Vꢀ ꢀ0.2Vꢀ
•ꢀ SSTL_2ꢀcompatibleꢀI/O
•ꢀ Double-dataꢀrateꢀarchitecture;ꢀtwoꢀdataꢀtransfersꢀ
perꢀclockꢀcycle
•ꢀ Bidirectional,ꢀdataꢀstrobeꢀ(DQS)ꢀisꢀtransmitted/
receivedꢀwithꢀdata,ꢀtoꢀbeꢀusedꢀinꢀcapturingꢀdataꢀ
atꢀtheꢀreceiver
•ꢀ DQSꢀisꢀedge-alignedꢀwithꢀdataꢀforꢀREADsꢀandꢀ
centre-alignedꢀwithꢀdataꢀforꢀWRITEs
•ꢀ Differentialꢀclockꢀinputsꢀ(CKꢀandꢀCK)
•ꢀ DLLꢀalignsꢀDQꢀandꢀDQSꢀtransitionsꢀwithꢀCKꢀ
transitions
•ꢀ CommandsꢀenteredꢀonꢀeachꢀpositiveꢀCKꢀedge;ꢀdataꢀ
andꢀdataꢀmaskꢀreferencedꢀtoꢀbothꢀedgesꢀofꢀDQS
•ꢀ Fourꢀinternalꢀbanksꢀforꢀconcurrentꢀoperation
ISSI’sꢀ256-MbitꢀDDRꢀSDRAMꢀachievesꢀhighꢀspeedꢀdataꢀ
transferꢀusingꢀpipelineꢀarchitectureꢀandꢀtwoꢀdataꢀwordꢀ
accessesꢀperꢀclockꢀcycle.ꢀTheꢀ268,435,456-bitꢀmemoryꢀ
arrayꢀisꢀinternallyꢀorganizedꢀasꢀfourꢀbanksꢀofꢀ64Mbꢀtoꢀ
allowꢀconcurrentꢀoperations.ꢀTheꢀpipelineꢀallowsꢀReadꢀ
andꢀWriteꢀburstꢀaccessesꢀtoꢀbeꢀvirtuallyꢀcontinuous,ꢀwithꢀ
theꢀoptionꢀtoꢀconcatenateꢀorꢀtruncateꢀtheꢀbursts.ꢀTheꢀ
programmableꢀfeaturesꢀofꢀburstꢀlength,ꢀburstꢀsequenceꢀ
andꢀCASꢀlatencyꢀenableꢀfurtherꢀadvantages.ꢀTheꢀdeviceꢀ
isꢀavailableꢀinꢀ8-bit,ꢀ16-bitꢀandꢀ32-bitꢀdataꢀwordꢀsizeꢀ
InputꢀdataꢀisꢀregisteredꢀonꢀtheꢀI/Oꢀpinsꢀonꢀbothꢀedgesꢀ
ofꢀDataꢀStrobeꢀsignal(s),ꢀwhileꢀoutputꢀdataꢀisꢀreferencedꢀ
toꢀbothꢀedgesꢀofꢀDataꢀStrobeꢀandꢀbothꢀedgesꢀofꢀCLK.ꢀ
CommandsꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgesꢀofꢀCLK.ꢀ
AnꢀAutoꢀRefreshꢀmodeꢀisꢀprovided,ꢀalongꢀwithꢀaꢀSelfꢀ
Refreshꢀmode.ꢀAllꢀI/OsꢀareꢀSSTL_2ꢀcompatible.
•ꢀ DataꢀMaskꢀforꢀwriteꢀdata.ꢀDMꢀmasksꢀwriteꢀdataꢀ
atꢀbothꢀrisingꢀandꢀfallingꢀedgesꢀofꢀdataꢀstrobe
ADDRESSꢀTABLE
Parameter
8Mꢀxꢀ32
16Mꢀxꢀ16
32Mꢀxꢀ8
•ꢀ BurstꢀLength:ꢀ2,ꢀ4ꢀandꢀ8
•ꢀ BurstꢀType:ꢀSequentialꢀandꢀInterleaveꢀmode
•ꢀ ProgrammableꢀCASꢀlatency:ꢀ2,ꢀ2.5ꢀandꢀ3ꢀ
•ꢀ AutoꢀRefreshꢀandꢀSelfꢀRefreshꢀModes
•ꢀ AutoꢀPrecharge
Configuration 2Mꢀxꢀ32ꢀxꢀ4ꢀ
banks
4Mꢀxꢀ16ꢀxꢀ4ꢀꢀ 8Mꢀxꢀ8ꢀxꢀ4ꢀꢀ
banks
banks
BankꢀAddressꢀ BA0,ꢀBA1
Pins
BA0,ꢀBA1
BA0,ꢀBA1
Autoprechargeꢀ A8/AP
Pins
A10/AP
A10/AP
•ꢀ TRASꢀLockoutꢀsupportedꢀ(tRAPꢀ=ꢀtRCD)
RowꢀAddress 4K(A0ꢀ–ꢀA11) 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)
OPTIONS
Columnꢀ
Address
512(A0ꢀ–ꢀA7,ꢀ 512(A0ꢀ–ꢀA8) 1K(A0ꢀ–ꢀA9)
A9)
•ꢀ Configuration(s):ꢀ8Mx32,ꢀ16Mx16,ꢀ32Mx8
•ꢀ Package(s):ꢀ
ꢀ 144ꢀBallꢀBGAꢀ(x32)
RefreshꢀCountꢀ
ꢀ
ꢀ
ꢀ
Com./Ind./A1ꢀ 4Kꢀ/ꢀ64msꢀ
A2 4Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64msꢀ
8Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64ms
ꢀ
66-pinꢀTSOP-IIꢀ(x8,ꢀx16)ꢀandꢀ60ꢀBallꢀBGAꢀ(x8,ꢀx16)
•ꢀ Lead-freeꢀpackageꢀavailable
•ꢀ TemperatureꢀRange:ꢀ
ꢀ Commercialꢀ(0°Cꢀtoꢀ+70°C)
KEYꢀTIMINGꢀPARAMETERS
SpeedꢀGradeꢀ
-5ꢀ
-6ꢀ
ꢀUnitsꢀ
ꢀ
ꢀ Industrialꢀ(-40°Cꢀtoꢀ+85°C)ꢀ
Automotive,ꢀA1ꢀ(-40°Cꢀtoꢀ+85°C)ꢀ
Automotive,ꢀA2ꢀ(-40°Cꢀtoꢀ+105°C)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
F
F
F
CkꢀMaxꢀCLꢀ=ꢀ3ꢀ
CkꢀMaxꢀCLꢀ=ꢀ2.5ꢀ
CkꢀMaxꢀCLꢀ=ꢀ2ꢀ
200ꢀ
200ꢀ
133ꢀ
167ꢀ
167ꢀ
133ꢀ
ꢀ MHz
ꢀ MHz
ꢀ MHz
Copyrightꢀ©ꢀ2012ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀ
notice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlat-
estꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreason-
ablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀ
unlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances
Integrated Silicon Solution, Inc. ꢀ
1
Rev.ꢀ B
06/19/2012
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