IS43/46R83200F
IS43/46R16160F
IS43/46R32800F
8Mx32, 16Mx16, 32Mx8
256Mb DDR SDRAM
FEATURES
• VDD and VDDQ: 2.5V 0.2V
• SSTL_2 compatible I/O
• Double-data rate architecture; two data transfers
per clock cycle
• Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
• DQS is edge-aligned with data for READs and
centre-aligned with data for WRITEs
®
Long-term Support
World Class Quality
AUGUST 2020
DEVICE OVERVIEW
ISSI’s 256-Mbit DDR SDRAM achieves high speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 268,435,456-bit memory
array is internally organized as four banks of 64Mb to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 8-bit, 16-bit and 32-bit data word size
Input data is registered on the I/O pins on both edges
of Data Strobe signal(s), while output data is referenced
to both edges of Data Strobe and both edges of CLK.
Commands are registered on the positive edges of CLK.
• Differential clock inputs (CK and CK)
• DLL aligns DQ and DQS transitions with CK
transitions
An Auto Refresh mode is provided, along with a Self
Refresh mode. All I/Os are SSTL_2 compatible.
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
ADDRESS TABLE
• Four internal banks for concurrent operation
Parameter
8M x 32
16M x 16
32M x 8
• Data Mask for write data. DM masks write data
at both rising and falling edges of data strobe
• Burst Length: 2, 4 and 8
Configuration 2M x 32 x 4
banks
4M x 16 x 4
banks
8M x 8 x 4
banks
• Burst Type: Sequential and Interleave mode
• Programmable CAS latency: 2, 2.5 and 3
• Auto Refresh and Self Refresh Modes
• Concurrent Auto Precharge supported
• TRAS Lockout supported (tRAP = tRCD)
Bank Address BA0, BA1
Pins
BA0, BA1
BA0, BA1
Autoprecharge A8/AP
Pins
A10/AP
A10/AP
Row Address 4K(A0 – A11) 8K(A0 – A12) 8K(A0 – A12)
Column
Address
512(A0 – A7, 512(A0 – A8) 1K(A0 – A9)
A9)
OPTIONS
Refresh Count
Com./Ind./A1 4K / 64ms
A2 4K / 16ms
• Configuration(s): 8Mx32, 16Mx16, 32Mx8
8K / 64ms
8K / 16ms
8K / 64ms
• Package(s):
144 Ball BGA (x32)
66-pin TSOP-II (x8, x16) and 60 Ball BGA (x8, x16)
• Lead-free package
• Temperature Range:
KEY TIMING PARAMETERS
Speed Grade
-5
-6
Units
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Automotive, A1 (-40°C to +85°C)
Automotive, A2 (-40°C to +105°C)
FCk Max CL = 3
FCk Max CL = 2.5
FCk Max CL = 2
200
167
133
167
167
133
MHz
MHz
MHz
Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
1
Rev. C1
08/26/2020
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