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IS43R16320A-5TL PDF预览

IS43R16320A-5TL

更新时间: 2024-11-21 20:07:19
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器双倍数据速率光电二极管内存集成电路
页数 文件大小 规格书
18页 460K
描述
DDR DRAM, 32MX16, 0.65ns, CMOS, PDSO66, LEAD FREE, TSOP2-66

IS43R16320A-5TL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSSOP,针数:66
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.28风险等级:5.22
访问模式:FOUR BANK PAGE BURST最长访问时间:0.65 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PDSO-G66
JESD-609代码:e3长度:22.22 mm
内存密度:536870912 bit内存集成电路类型:DDR DRAM
内存宽度:16湿度敏感等级:3
功能数量:1端口数量:1
端子数量:66字数:33554432 words
字数代码:32000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32MX16封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
自我刷新:YES最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.5 V标称供电电压 (Vsup):2.6 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:10.16 mmBase Number Matches:1

IS43R16320A-5TL 数据手册

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®
IS43R16320A  
ISSI  
NOVEMBER 2006  
32Meg x 16  
512-MBIT DDR SDRAM  
FEATURES  
DEVICE OVERVIEW  
Clock Frequency: 166, 200 MHz  
ISSI’s 512-Mbit DDR SDRAM achieves high-speed data  
transfer using pipeline architecture and two data word  
accesses per clock cycle. The 536,870,912-bit memory  
array is internally organized as four banks of 128M-bit to  
allowconcurrentoperations. ThepipelineallowsRead  
and Write burst accesses to be virtually continuous, with  
the option to concatenate or truncate the bursts. The  
programmable features of burst length, burst sequence  
and CAS latency enable further advantages. The device  
is available in 16-bit data word size. Input data is regis-  
tered on the I/O pins on both edges of Data Strobe  
signal(s), while output data is referenced to both edges of  
Data Strobe and both edges of CK. Commands are  
registered on the positive edges of CK. Auto Refresh,  
Active Power Down, and Pre-charge Power Down modes  
are enabled by using clock enable (CKE) and other  
inputs in an industry-standard sequence. All input and  
output voltage levels are compatible with SSTL 2.  
Power supply (VDD and VDDQ)  
DDR 333: 2.5V + 0.2V  
DDR 400: 2.6V + 0.1V  
SSTL 2 interface  
Four internal banks to hide row Pre-charge  
and Active operations  
Commands and addresses register on positive  
clock edges (CK)  
Bi-directional Data Strobe signal for data cap-  
ture  
Differential clock inputs (CK and CK) for  
two data accesses per clock cycle  
Data Mask feature for Writes supported  
DLL aligns data I/O and Data Strobe transitions  
with clock inputs  
KEY TIMING PARAMETERS  
Programmable burst length for Read and Write  
operations  
Parameter  
-5  
-6  
Unit  
Programmable CAS Latency  
2/2.5 (6K), 2.5/3 (5T)  
Programmable burst sequence: sequential or  
interleaved  
DDR400 DDR333  
Clock Cycle Time  
CASLatency=3  
CASLatency=2.5  
CASLatency=2  
5
6
6
7.5  
ns  
ns  
ns  
Burst concatenation and truncation supported  
for maximum data throughput  
Auto Pre-charge option for each Read or Write  
burst  
ClockFrequency  
CASLatency=3  
CASLatency=2.5  
CASLatency=2  
200  
166  
166  
133  
MHz  
MHz  
MHz  
8192 refresh cycles every 64ms  
Auto Refresh and Self Refresh Modes  
Pre-charge Power Down and Active Power  
Down Modes  
Lead-free package  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
Rev. B  
11/10/06  

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