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IS42S16160D-75EBL-TR PDF预览

IS42S16160D-75EBL-TR

更新时间: 2024-01-03 11:56:24
品牌 Logo 应用领域
美国芯成 - ISSI 时钟动态存储器内存集成电路
页数 文件大小 规格书
64页 926K
描述
Synchronous DRAM, 16MX16, 5.5ns, CMOS, PBGA54

IS42S16160D-75EBL-TR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.83
最长访问时间:5.5 ns最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:S-PBGA-B54内存密度:268435456 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
端子数量:54字数:16777216 words
字数代码:16000000最高工作温度:70 °C
最低工作温度:组织:16MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA54,9X9,32
封装形状:SQUARE封装形式:GRID ARRAY, FINE PITCH
电源:3.3 V认证状态:Not Qualified
刷新周期:8192连续突发长度:1,2,4,8,FP
最大待机电流:0.003 A子类别:DRAMs
最大压摆率:0.18 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
Base Number Matches:1

IS42S16160D-75EBL-TR 数据手册

 浏览型号IS42S16160D-75EBL-TR的Datasheet PDF文件第2页浏览型号IS42S16160D-75EBL-TR的Datasheet PDF文件第3页浏览型号IS42S16160D-75EBL-TR的Datasheet PDF文件第4页浏览型号IS42S16160D-75EBL-TR的Datasheet PDF文件第5页浏览型号IS42S16160D-75EBL-TR的Datasheet PDF文件第6页浏览型号IS42S16160D-75EBL-TR的Datasheet PDF文件第7页 
IS42S83200D, IS42S16160D  
IS45S83200D, IS45S16160D  
32Megꢀxꢀ8,ꢀꢀ16Megꢀx16ꢀ  
256-MBITꢀSYNCHRONOUSꢀDRAM  
DECEMBERꢀ2011  
OVERVIEW  
FEATURES  
ISSI'sꢀ256MbꢀSynchronousꢀDRAMꢀꢀachievesꢀhigh-speedꢀ  
dataꢀtransferꢀusingꢀpipelineꢀarchitecture.ꢀꢀAllꢀinputsꢀandꢀ  
outputsꢀsignalsꢀreferꢀꢀtoꢀtheꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀ  
Theꢀ256MbꢀSDRAMꢀisꢀorganizedꢀasꢀfollows.ꢀ  
•ꢀ Clockꢀfrequency:ꢀ166,ꢀ143ꢀꢀMHz  
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ  
positiveꢀclockꢀedge  
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge  
•ꢀ SingleꢀPowerꢀsupply:ꢀ3.3Vꢀ+ꢀ0.3Vꢀ  
•ꢀ LVTTLꢀinterface  
IS42S83200Dꢀ  
IS42S16160Dꢀ  
8Mꢀxꢀ8ꢀxꢀ4ꢀBanksꢀ 4Mꢀx16x4ꢀBanksꢀ  
54-pinꢀTSOPIIꢀ  
54-ballꢀBGAꢀ  
54-pinꢀTSOPII  
54-ballꢀBGAꢀ  
•ꢀ Programmableꢀburstꢀlengthꢀꢀ  
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)  
ꢀ ꢀ  
•ꢀ Programmableꢀburstꢀsequence:ꢀꢀ  
Sequential/Interleaveꢀ  
KEYTIMINGꢀPARAMETERS  
Parameterꢀ  
-6ꢀ  
-7ꢀ -75Eꢀ Unit  
•ꢀ AutoꢀRefreshꢀ(CBR)  
•ꢀ SelfꢀRefresh  
ClkꢀCycleꢀTimeꢀ  
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ  
ꢀ CASꢀLatencyꢀ=ꢀ2ꢀ  
ꢀꢀ  
6ꢀ  
10ꢀ  
7ꢀ  
10ꢀ  
—ꢀ  
7.5ꢀ  
nsꢀ  
ns  
•ꢀ 8Kꢀrefreshꢀcyclesꢀeveryꢀ16ꢀmsꢀ(A2ꢀgrade)ꢀorꢀꢀ  
64ꢀmsꢀ(commercial,ꢀindustrial,ꢀA1ꢀgrade)  
ClkꢀFrequencyꢀ  
ꢀꢀ  
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ  
ꢀ CASꢀLatencyꢀ=ꢀ2ꢀ  
166ꢀ  
100ꢀ  
143ꢀ  
100ꢀ  
—ꢀ  
133ꢀ  
Mhzꢀ  
Mhz  
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle  
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)  
AccessꢀTimeꢀꢀfromꢀClockꢀ  
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ  
ꢀ CASꢀLatencyꢀ=ꢀ2ꢀ  
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀꢀ  
operationsꢀcapability  
5.4ꢀ  
6.5ꢀ  
5.4ꢀ  
6.5ꢀ  
—ꢀ  
5.5ꢀ  
nsꢀ  
ns  
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ  
command  
ADDRESSTABLE  
OPTIONS  
Parameter  
32M x 8  
16M x 16  
•ꢀ Package:ꢀ  
54-pinꢀTSOP-IIꢀ  
54-ballꢀBGA  
Configuration  
8M x 8 x 4  
banks  
4M x 16 x 4  
banks  
Refresh Count  
Com./Ind. 8K/64ms  
A1 8K/64ms  
8K/64ms  
8K/64ms  
8K/16ms  
•ꢀ OperatingꢀTemperatureꢀRange:ꢀ  
Commercialꢀ(0oCꢀtoꢀ+70oC)  
A2 8K/16ms  
Industrialꢀ(-40oCꢀtoꢀ+85oC)  
Row Addresses  
A0-A12  
A0-A12  
A0-A8  
AutomotiveꢀGradeꢀA1ꢀ(-40oCꢀtoꢀ+85oC)  
AutomotiveꢀGradeꢀA2ꢀ(-40oCꢀtoꢀ+105oC)  
Column Addresses  
Bank Address Pins  
Auto Precharge Pins  
A0-A9  
BA0, BA1  
A10/AP  
BA0, BA1  
A10/AP  
Copyrightꢀ©ꢀ2010ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwith-  
outꢀnotice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀ  
theꢀlatestꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ  
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀ  
reasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀap-  
plicationsꢀunlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:  
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;  
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand  
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
1
Rev.ꢀ E  
12/01/2011  

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