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IS42RM32800D-7TL PDF预览

IS42RM32800D-7TL

更新时间: 2024-11-14 04:56:51
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
24页 506K
描述
Synchronous DRAM, 8MX32, 5.4ns, CMOS, PDSO86, LEAD FREE, PLASTIC, TSOP2-86

IS42RM32800D-7TL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2,针数:86
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.24风险等级:5.73
访问模式:FOUR BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PDSO-G86
JESD-609代码:e3长度:22.22 mm
内存密度:268435456 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:32湿度敏感等级:3
功能数量:1端口数量:1
端子数量:86字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8MX32封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
自我刷新:YES最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:10
宽度:10.16 mmBase Number Matches:1

IS42RM32800D-7TL 数据手册

 浏览型号IS42RM32800D-7TL的Datasheet PDF文件第2页浏览型号IS42RM32800D-7TL的Datasheet PDF文件第3页浏览型号IS42RM32800D-7TL的Datasheet PDF文件第4页浏览型号IS42RM32800D-7TL的Datasheet PDF文件第5页浏览型号IS42RM32800D-7TL的Datasheet PDF文件第6页浏览型号IS42RM32800D-7TL的Datasheet PDF文件第7页 
IS42SM83200D / IS42SM16160D / IS42SM32800D  
IS42RM83200D / IS42RM16160D / IS42RM32800D  
32Mx8, 16Mx16, 8Mx32  
256Mb Mobile Synchronous DRAM  
Preliminary Information  
JULY 2008  
DESCRIPTION  
FEATURES  
ISSI's 256Mb Mobile Synchronous DRAM achieves high-  
speed data transfer using pipeline architecture. All input  
and output signals refer to the rising edge of the clock  
input. Both write and read accesses to the SDRAM are  
burst oriented. The 256Mb Mobile Synchronous DRAM  
is designed to minimize current consumption making it  
ideal for low-power applications. Both TSOP and BGA  
packages are offered, including industrial grade products.  
•ꢀ Fully synchronous; all signals referenced to a  
positive clock edge  
•ꢀ Internal bank for hiding row access and pre-  
charge  
•ꢀ Programmable CAS latency: 2, 3  
•ꢀ Programmable Burst Length: 1, 2, 4, 8, and Full  
Page  
•ꢀ Programmable Burst Sequence:  
•ꢀ Sequential and Interleave  
•ꢀ Auto Refresh (CBR)  
KEY TIMING PARAMETERS  
Parameter  
-6  
-7  
-75E  
Unit  
•ꢀ TCSR (Temperature Compensated Self Refresh)  
CLK Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
CLK Frequency  
CAS Latency = 3  
CAS Latency = 2  
Access Time from CLK  
CAS Latency = 3  
CAS Latency = 2  
•ꢀ PASR (Partial Arrays Self Refresh): 1/16, 1/8,  
1/4, 1/2, and Full  
•ꢀ Deep Power Down Mode (DPD)  
6
7
ns  
ns  
10  
10  
7.5  
•ꢀ Driver Strength Control (DS): 1/4, 1/2, and Full  
166  
100  
143  
100  
Mhz  
Mhz  
OPTIONS  
•ꢀ Configurations:  
- 32M x 8  
133  
5.4  
6.5  
5.4  
6.5  
ns  
ns  
- 16M x 16  
- 8M x 32  
5.5  
•ꢀ Power Supply  
IS42SMxxx – Vd d /Vd d q = 3.3 V  
IS42RMxxx – Vd d /Vd d q = 2.5 V  
•ꢀ Packages:  
x8 / x16 –TSOP II (54), BGA (54) [x16 only]  
x32 – TSOP II (86), BGA (90)  
•ꢀ Temperature Range:  
Commercial (0°C to +70°C)  
Industrial (–40 ºC to 85 ºC)  
•ꢀ Die Revision: D  
ADDRESSING TABLE  
Parameter  
32M x 8  
8M x 8 x 4 banks  
8K/64ms  
A0-A12  
16M x 16  
4M x 16 x 4 banks  
8K/64ms  
8M x 32  
Configuration  
2M x 32 x 4 banks  
4K/64ms  
A0-A11  
Refresh Count  
Row Addressing  
Column Addressing  
Bank Addressing  
Precharge Addressing  
A0-A12  
A0-A9  
A0-A8  
A0-A8  
BA0, BA1  
A10  
BA0, BA1  
A10  
BA0, BA1  
A10  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-  
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain  
the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. - www.issi.com  
Rev. 00A  
1
06/04/08  

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