OptiMOS™3ꢀPowerꢀMOSꢀTransistorꢀChip
IPC055N03L3
PowerꢀMOSꢀTransistorꢀChip
1ꢀꢀꢀꢀꢀDescription
•ꢀN-channelꢀenhancementꢀmode
•ꢀForꢀdynamicꢀcharacterizationꢀreferꢀtoꢀtheꢀdatasheetꢀofꢀIPD031N03LG
•ꢀAQLꢀ0.65ꢀforꢀvisualꢀinspectionꢀaccordingꢀtoꢀfailureꢀcatalogue
•ꢀElectrostaticꢀDischargeꢀSensitiveꢀDeviceꢀaccordingꢀtoꢀMIL-STDꢀ883C
•ꢀDieꢀbond:ꢀsolderedꢀorꢀglued
•ꢀBacksideꢀmetallization:ꢀNiVꢀsystem
•ꢀFrontsideꢀmetallization:ꢀAlCuꢀsystem
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters
Parameter
Value
Unit
V(BR)DSS
30
V
Drain
RDS(on)
3.11)
mΩ
mm2
µm
Die size
Thickness
3.28 x 1.68
175
Gate
Source
Typeꢀ/ꢀOrderingꢀCode
Package
Chip
Marking
RelatedꢀLinks
IPC055N03L3
not defined
-
2ꢀꢀꢀꢀꢀElectricalꢀCharacteristicsꢀonꢀWaferꢀLevel
atꢀTjꢀ=ꢀ25°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ2ꢀꢀꢀꢀꢀ
Values
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Typ.
Max.
-
Drain-source breakdown voltage
Gate threshold voltage
V(BR)DSS
VGS(th)
IDSS
30
1
-
-
-
-
-
V
VGS=0ꢀVꢀ,ID=1ꢀmA
VDS=VGS,ꢀID=250ꢀµA
VGS=0ꢀVꢀ,VDS=30ꢀV
VGS=20ꢀVꢀ,VDS=0ꢀV
2.2
1
V
Zero gate voltage drain current
Gate-source leakage current
µA
nA
IGSS
-
100
-
-
2.72)
1.72)
503)
503)
VGS=4.5ꢀVꢀ,ID=2.0ꢀA
VGS=10ꢀVꢀ,ID=2.0ꢀA
Drain-source on- resistance
RDS(on)
mΩ
Reverse diode forward on-voltage
Avalanche energy, single pulse
VSD
EAS
-
-
0.82
-
1.1
90
V
VGS=0ꢀVꢀ,IF=1A
mJ
ID =50 A, RGS =25 Ω
1) packaged in a DPAK using Al bond wire (see ref. product)
2)ꢀtypicalꢀbareꢀdieꢀRDS(on);ꢀVGS=10ꢀVꢀwhenꢀusedꢀwithꢀ4x500µmꢀAl-wedgeꢀdouble-stitchꢀbonding
3) limited by wafer test-equipment
Final Data Sheet
2
Rev.ꢀ2.5,ꢀꢀ2014-07-25