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IN74ACT109N PDF预览

IN74ACT109N

更新时间: 2024-09-15 22:48:07
品牌 Logo 应用领域
INTEGRAL 触发器锁存器
页数 文件大小 规格书
5页 185K
描述
DUAL J-K FLIP-FLOP WITH SET AND RESET

IN74ACT109N 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.75
Is Samacsys:NBase Number Matches:1

IN74ACT109N 数据手册

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IN74ACT109  
DUAL J-K FLIP-FLOP  
WITH SET AND RESET  
High-Speed Silicon-Gate CMOS  
The IN74ACT109 is identical in pinout to the LS/ALS109,  
HC/HCT109. The IN74ACT109 may be used as a level converter  
for interfacing TTL or NMOS outputs to High Speed CMOS inputs.  
This device consists of two J-K flip-flops with individual set,  
reset, and clock inputs. Changes at the inputs are reflected at the  
outputs with the next low-to-high transition of the clock. Both Q to  
Q outputs are available from each flip-flop.  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
ORDERING INFORMATION  
IN74ACT109N Plastic  
IN74ACT109D SOIC  
TA = -40° to 85° C for all  
packages  
Low Input Current: 1.0 µA; 0.1 µA @ 25°C  
Outputs Source/Sink 24 mA  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
FUNCTION TABLE  
Inputs  
Outputs  
Set Reset Clock  
J
X
X
X
L
K
X
X
X
L
Q
Q
L
L
H
L
H
L
X
X
X
H
L
H
H*  
H
L
H*  
L
H
H
H
H
H
H
H
H
H
H
H
L
L
Toggle  
H
H
X
No Change  
H
X
H
L
L
No Change  
X = Don’t care  
PIN 16=VCC  
*Both outputs will remain high as long as  
Set and Reset are low, but the output  
states are unpredictable if Set and Reset  
go high simultaneously.  
PIN 8 = GND  
1

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